This brief presents a bulk-driven transconductance cell using a basic self-biasing current generator circuit. The proposed cell employs two N-type and P-type current mirrors to form a positive feedback structure. The circuit is adaptively biased by diode-connected topologies of the current mirrors. The bulk terminals of the P-type transistors act as the input nodes to employ the proposed circuit as a transconductance cell. Thanks to its symmetrical self-biasing topology, a tailed double-output differential structure is achieved. An additional current source is also used to ensure the stability and adjust the amount of the produced transconductance. The circuit is simulated using a 0.18-µm CMOS technology to verify its operation.
Short Report
The Self-Biasing Current Generator: A Useful Transconductance Cell
https://doi.org/10.21203/rs.3.rs-4971100/v1
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Transconductance cell
Ultra-low-power
Positive feedback
Current generator
Self-biasing
Bulk-driven
TRANSCONDUCTANCE cells are widely used in analog and mixed-signal circuits such as operational transconductance amplifiers (OTA) [1], rail-to-rail circuits [2], tunable filters [3, 4], etc. Among all these circuits, the ultra-low-power (ULP) OTAs are widely used because of their capability of playing the role of many different functions. Recently, several OTAs have been enhanced based on the positive feedback topologies in [5, 6], which are suitable for ultra-low-voltage (ULV) applications. In this way, bulk terminals of the differential pair topology were used as the input nodes to provide a high input dynamic range. Nonetheless, due to a lower bulk transconductance than that of the gate terminal, designers face some disadvantages such as lower gain bandwidth (GBW), lower DC gain, lower slew rate (SR), larger input noise, and larger offset, which were carefully analyzed and reduced in [5–7].
Figure 1 (a) shows the basic idea of a conventional current generator circuit, which its performance can be improved by adding a resistance at the source terminal of transistor M4 [8]. This circuit forms a positive feedback loop and will be stable for a loop gain less than unity. This structure is very useful to design a transconductance cell with a self-biasing topology.
Figure 1 (b) shows the proposed self-biasing transconductance cell [9]. As is seen, transistor M0 is added as the tail current to create a virtual ground at the source of M1-M2, which results in a special differential pair. Based on the analysis done in [9], having a tail current will increase the common-mode-rejection ratio (CMRR) of the structure. This circuit can only be converted to a bulk-driven transconductance cell because there is no more idle terminal to be used as the input node except bulks. Therefore, the bulk terminals of P-type transistors M1-M2 are used as the input nodes that offer a high input dynamic range.
To stabilize the proposed structure, an adjustable current source, M5, should be paralleled with one of the non-diode-connected transistors M2-M3. Actually, without employing M5, the proposed structure provides an infinite output impedance casing an unstable behavior in the transient response. Eq. (1) expresses the impedance seen from both outputs where its amount is adjusted by the transconductance of M5, gm5, and the pole associated with output nodes can be moved by tuning Vb2.
$${R_{out \pm }} \approx \frac{1}{{g{m_1}\left( {1 - \frac{{g{m_2}\left( {g{m_1} - g{m_5}} \right)}}{{g{m_1}g{m_4}}}} \right)}}$$
1
where gmi represents the transconductance of the corresponding transistors, and (gm1-gm5) = gm3. Therefore, to achieve a finite positive impedance at the output, gm5 should have a non-zero value. It is obvious that the proposed structure benefits from a high output impedance, which results in a higher transconductance and a larger DC gain in comparison with a conventional bulk-driven structure. In addition, the proposed cell provides a double-ended structure, while the output common mode voltages are controlled by its self-biasing topology without employing any common-mode feedback (CMFB) circuit. By employing two of the proposed cells, a self-biasing high-performance transconductance amplifier can easily be designed as a tunable high dynamic range circuit.
The proposed circuit was simulated in TSMC 0.18 µm CMOS technology @ 0.4 V driving a 2×2 pF capacitive load. The frequency response of the amplifier is shown in Fig. 2, while a DC gain and a gain bandwidth of 25 dB and 3 kHz were respectively achieved. To simulate the step response, a unity-gain capacitive buffer employed in [10] was used. In this way, a large differential step of 0.2V at 50 kHz was applied to the inputs. Fig. 3 shows the step response of the amplifier representing an average slew rate of 32 V/ms. Thanks to the use of the bulk-driven method, Fig. 3 also shows that a differential input/output voltage swing of 0.4V was achieved. Table 1 reports the main specifications of the proposed transconductance cell, while it consumes just 4 nW power. As a result, the proposed circuit can be very useful in configuring a high-performance bulk-driven transconductance amplifier, specially those that operate under sub-threshold supplies with a self-biasing topology.
This brief re-configured a basic self-biasing current generator circuit as a high-performance transconductance cell. The proposed structure used the bulk terminals of P-type transistors as the input nodes to provide a high input dynamic range. To stabilize the circuit, an additional transistor was used as a shunt-current method to finite the output impedance. The circuit was designed and simulated in TSMC 0.18 µm CMOS technology under a supply voltage of 0.4 V. Simulation results showed a DC gain of 25 dB and an average slew rate of 32 V/ms for a capacitive load of 2×2 pF.
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Table 1: Specifications of the proposed transconductance cell.
The authors declare no competing interests.