An analysis of the eddy effect in through-silicon vias based on Cu and CNT bundles: the impact on crosstalk and power

The performance of three-dimensional integrated circuits primarily depends on the filler material used in the through-silicon vias (TSVs). The most widely used filler material is Cu, but it faces severe reliability issues due to the skin effect and problems related to electromigration at high frequencies. Therefore, single- and multiwalled carbon nanotube (SWCNT and MWCNT) bundles have recently emerged as suitable filler materials for TSVs. Additionally, at high frequencies, electromagnetic forces induce eddy currents that adversely affect the overall performance of TSVs. This paper demonstrates for the first time the impact of eddy currents on TSVs based on Cu as well as SWCNT and MWCNT bundles. An accurate RLGC circuit model is proposed by considering the eddy effect at the depletion layer, neighboring TSVs and in the silicon substrate region. The resulting closed-form expressions for the TSV parasitic parameters are verified against previous experimental data obtained at an operating frequency of 2 GHz. Good agreement between the experimental and analytical data for the resistance and inductance is observed, revealing a difference of approximately 8.02% and 4.95%, respectively. The equivalent circuit parameters are modeled at the 7-nm technology node using a three-line driver-via-load setup. For the proposed setup, the crosstalk-induced delay, the peak noise voltage, and the power dissipation are analyzed with and without consideration of the eddy effect. Irrespective of the TSV height, the MWCNT bundle design demonstrates substantially lower crosstalk delay, peak noise, and power dissipation in comparison with the TSVs based on Cu or SWCNT bundles. The overall difference when including the eddy effect is approximately 16.55%, 2.45%, and 0.27% for the crosstalk delay, noise voltage, and power dissipation, respectively. Furthermore, to demonstrate the complexity of the model at smaller technology nodes, a comprehensive study is performed at the 5-nm and 7-nm technology nodes. It is observed that the delay without the eddy effect at the 5-nm technology node is higher on average by 3.4-fold for Cu, whereas for the TSVs based on MWCNT bundles it is only 2.6-fold higher.


Introduction
Recently, the through-silicon vias (TSVs) in three-dimensional integrated circuits have attracted extensive attention due to their higher packaging density and bandwidth [1,2], low latency [3], and homogeneous and heterogeneous integration [4,5]. Mostly, copper (Cu) is used as the filler material in TSVs due to its better conductivity and comparative compatibility with the via-last TSV fabrication process [6]. However, challenges due to fabrication limitations in accomplishing physical vapor deposition (PVD) and seed layer deposition for Cu-based TSVs have driven researchers to introduce carbon nanotubes (CNTs) as an alternative filler material. CNTs are hollow cylindrical structures made up of graphene sheets rolled up concentrically at a specific angle [7]. Two types of CNTs, viz. single-(SWCNT) and multiwalled CNTs (MWCNT), are generally preferred as filler materials. Their negligible electromigration and thermal stability, and unique electrical and mechanical properties give CNTs an edge over other TSV filler materials for use in nanotechnology [8]. However, the performance of TSVs at the nanometer level is affected by several deepsubmicron effects such as short-channel effects including the reverse short-channel effect, poly depletion and the surface charge centroid effect, the narrow-channel effect, the reverse narrow-channel effect, the leakage current effect, the draininduced barrier lowering effect, and the hot carrier effect. At smaller technology nodes, the physical dimensions of TSVs are reduced, which improves the device density and operating frequency of such ICs. However, the diffusion of metal from the TSV to the silicon substrate increases as the channel length is reduced. Due to this reduced channel length, the channel electric field becomes more significant, which is the primary reason for the hot carrier effect. The charge carriers can then gain sufficient kinetic energy to break the barrier between the TSV and the silicon substrate. Some negative short-channel effects include the drain-induced barrier lowering, velocity saturation, and quantum confinement [9]. Usually, the threshold voltage reduces with the channel length due to such short-channel effects. In the reverse short-channel effect, the threshold voltage increases for a reduced channel length due to the nonuniform doping profile used in device manufacturing at the deep-submicron level. However, this higher threshold requires a higher gate voltage [10]. Thus, severe challenges are introduced in TSVs when moving towards smaller technology nodes. Furthermore, at smaller technology nodes, the eddy resistance plays a key role in the high-frequency modeling of TSVs. According to Faraday's law of induction and Lenz's law [11,12], the eddy current is circulatory in nature because it opposes the change in the magnetic field. Hence, an eddy resistance occurs at high frequency.
In general, most state-of-the-art experimental evidence [13][14][15][16][17][18][19][20][21][22] describes equivalent RLGC models for cylindricalshaped TSVs. Previously, researchers [13,14] reported a comparative study on the propagation delay of TSVs with different filler materials such as Cu or SWCNT and MWCNT bundles but neglecting the eddy effect in the depletion layer and neighboring TSVs. Later, Kim et al. [15] presented a compact alternating-current (AC) model of a TSV including the via bump, redistribution layers, and skin effect. That analysis was based on an eye diagram using the method described in Ref. [16]. However, the impact of the eddy effect has been ignored in TSV modeling. Some researchers [17,18] have proposed comprehensive models for TSVs based on SWCNT bundles, describing a significant improvement in the delay and power performance. However, those authors did not carry out high-frequency analysis. Later, Su et al. [19] proposed an equivalent model of MWCNT-based TSV that considered the eddy effect only in the substrate region. Lu et al. [20] demonstrated a pi equivalent electrical model of the Cu-based TSV with consideration of eddy currents and the proximity effect at high frequencies. However, those authors restricted their research to the impact of the eddy effect on only the power loss of the TSV. Later, Liao et al. [21] demonstrated the crosstalk-induced delay by considering the proximity effect in a shielded paired TSV. However, the impact of the eddy effect was restricted to only the silicon substrate. Recently, researchers [22] demonstrated the delay and power dissipation for differently shaped TSVs while considering the skin effect at high frequency. However, the mutual inductance, eddy resistance, and depletion capacitance were ignored. Therefore, current state-of-the-art research [13][14][15][16][17][18][19][20][21][22] fails to enable a comprehensive analysis of the eddy effect for TSVs at high frequencies, hence a detailed investigation is required to clarify the eddy resistance of TSVs.
This study demonstrates, for the first time, electrical modeling of TSVs with consideration of the eddy effect at high frequencies. To demonstrate this effect, a closed-form expression is derived for the eddy resistance in the depletion region, silicon substrate, and neighboring TSVs. In addition, the metal oxide semiconductor (MOS) effect is also considered during the RLGC modeling of the TSV. Furthermore, the liner and the depletion layers are used to provide isolation to the TSV from the silicon substrate. Similarly, intermetal dielectric (IMD) and underfilled layers are included to isolate the bump from the silicon substrate and to prevent coupling between the bumps, respectively. This paper analyzes the crosstalk and power performance using a threeline parallel driver-via-load (DVL) setup, wherein via lines with Cu, SWCNT, and MWCNT bundles as filler material are modeled. The model primarily considers the impact of the eddy effect at the 7-nm technology node [23]. The main reason behind choosing a this node is that it provides higher device density, improved power savings, and better performance. A unique setup with 20 distributed pi-type networks is used for the electrical circuit model. A pi-type distributed network is considered instead of L-or T-type networks due to performance accuracy considerations [24,25]. Thereafter, to demonstrate the complexity of the model at lower technology nodes, a comprehensive analysis of the crosstalk and power is also performed at the 5-nm technology node.
This manuscript is organized into the following sections: Sect. 1 sheds light on the recent state-of-art research scenario and summarizes the modeling of cylindrical-shaped TSVs, taking into account the impact of the eddy resistance. Section 2 introduces the electrical equivalent model for the TSVs based on Cu, and SWCNT or MWCNT bundles (number of shells ,n = 10) with and without consideration 1 3 of the eddy resistance. A detailed analytical expression is derived to model the eddy resistance in the silicon substrate, depletion region, and neighboring TSVs. Based on the proposed model, Sect. 3 describes a comprehensive study of the impact of the eddy resistance on the crosstalk noise, delay, and power dissipation, considering different heights and frequencies. Finally, Sect. 4 briefly concludes this work with a summary.

The TSV model and eddy resistance
This section describes the cylindrical-shaped TSV structure and its physical parameters when using the different filler materials, viz. Cu, and SWCNT or MWCNT bundles. Furthermore, a closed-form expression is derived for the eddy resistance in the depletion region, the silicon substrate, and the neighboring TSVs. A novel equivalent electrical model for the cylindrical TSV is then proposed with consideration of the eddy resistance.

The structure and physical parameters of the TSV
This subsection provides a detailed description of the structure of the TSV and quantitative values for several of its parameters that will be used in the equivalent RLGC model. Figure 1a and b show the physical configuration and a top cross-sectional view of the cylindrical TSV, respectively. The TSV is surrounded by an insulating layer such as a liner (usually SiO 2 ) as well as depletion layers to provide directcurrent (DC) isolation and prevent leakage between the TSV and the substrate. Usually, copper is used as a filler material in the TSV and the bump. A cylindrical-shaped pillar bump is used to provide a contact between the TSVs and different functional blocks of the die. In general, an IMD and underfilled layer are used to isolate the bump from the substrate and to reduce the cross-coupling between the bumps, respectively. Lossy silicon material is considered as the substrate, whereas the depletion region consists of lossless silicon to reduce the leakage. Silica-filled anhydride resin polymers are used in the underfilled layer to prevent coupling between the bumps. The physical parameters of the cylindrical TSVs designed at the 7-and 5-nm technology nodes [26] are presented in Fig. 1 and Table 1. The number of CNTs in a bundle is primarily calculated using the cross-sectional area of the TSV and the diameter of the CNTs, as discussed below.

The Cu-based TSV model
This subsection describes the Cu-based TSV modeling with consideration of the eddy effect in the silicon substrate, depletion region, and neighboring TSVs. Firstly, a closedform expression for the eddy resistance in the silicon substrate is derived by using the physical dimensions of the TSV as shown in Fig. 1. The equivalent RLGC circuit model of the three-line TSV at high frequency is presented in Fig. 2. Whenever a high-frequency current passes through the TSV, it generates a varying magnetic field. Thus, the magnetic vector potential ⃗ A is calculated by using the Maxwell equation [28,29] as   where σ Si,eff = σ Si + jωμε Si is the effective conductivity of the silicon substrate and ω is the angular frequency. Assuming that the magnetic vector potential has only a z-directional component but varies in the radial direction r of the TSV, the variation in the ϕ and z directions will be zero in the cylindrical coordinate system. Therefore, ∂A z /∂z = 0, ∂A z /∂ϕ = 0 [30]. Equation (1) can thus be simplified to where k s = (−jωμ Si σ Si,eff ) 1/2 . Using the solution of the Bessel function, Eq. (2) can be simplified to where c 1 and c 2 are arbitrary constants, a 1 = r TSV + t liner + t dep , and b 1 = [p via − (r TSV + t liner + t dep )]. It is assumed that the total current I is passing through the TSV. Hence, Ampere's law can be used to obtain the magnetic vector potential in the depletion and insulating layers as where r TSV ≤ r ≤ a 1 or b 1 ≤ r ≤ (p via − r TSV ). Applying the boundary condition in the TSV as in Eq. (5) to Eq. (8) yields Now, c 1 and c 2 can be obtained after solving the above expressions as follows: where and (5) The electric current density in the substrate is J z sub (r), which can be derived from Eqs. (3), (9), and (10) as Hence, the eddy resistance in the substrate ( r ′ e_sub ) can be obtained by using Eq. (13) and can be expressed per unit height (p.u.h.) as where h = h tsv -2h IMD for the calculation of the eddy resistance over the total height. In the same way, the eddy resistance in the depletion region ( r ′ e_dep ) and the neighboring TSVs (r � e_sub ) can be obtained by using the limits of the radius and the material as (r TSV + t liner ) ≤ r ≤ (r TSV + t liner + t dep ) and (r TSV + t liner + t dep ) ≤ r ≤ [p via + (r TSV + t liner + t dep )], respectively. Values of t he conductivity of σ Si,dep = 1.56 × 10 -3 S/m in the depleted silicon region and σ Si = 100 S/m for the silicon substrate are considered herein.
As shown in Fig. 2, the other parasitic parameters of the TSV can be obtained by using its physical dimensions. First, the total capacitance (C uimd ) is a parallel combination of the underfill (C uf ) and IMD capacitances (C imd ). C uf occurs between pairs of bumps due to the presence of the underfilled layer made of silica-filled anhydride resin polymer. However, C imd occurs between pairs of TSVs due to the presence of the IMD layer [31]. C uf and C imd can be modeled as parallel-wire capacitances thus [15]: A capacitance corresponding to the silicon substrate ( c ′ sub ) occurs between the TSVs due to the presence of the conductive silicon substrate. c ′ sub p.u.h. can be derived using the parallel-wire capacitance model [32] as where the height is considered to be h = h tsv -2h IMD . In addition, the substrate conductance g ′ sub occurs between pairs of TSVs due to the lossy characteristics of the silicon substrate. g ′ sub can be obtained by using the relationship between c ′ sub and g ′ sub as discussed in ref. [15]. The liner capacitance c ′ liner occurs between the TSV and depletion layer due to the presence of the oxide layer [15]. In addition, the depletion capacitance c ′ d occurs between the TSVs surrounded by the oxide layer and the Si substrate in the presence of the depletion layer [32]. c ′ liner and c ′ d p.u.h. can be derived by applying the coaxial-wire capacitance model.
The bump capacitance c ′ b occurs between the silicon substrate and the bump due to the presence of the IMD layer. The bump capacitance p.u.h. can be expressed by using the parallel-plate capacitor model [15] as Moreover, the total resistance of the circuit r ′ t in Fig. 2 is a series combination of the TSV resistance r ′ tsv and the bump resistance r ′ b : where r ′ tsv and r ′ b are obtained using the DC and AC components of the resistance p.u.h. Here, the AC component of the resistance primarily considers the skin effect of the TSV [15]. On the other hand, the total inductance l ′ t is a series combination of the bump inductance l ′ b and the TSV inductance l ′ tsv [15]. The inductance occurs due to the magnetic field produced by the current passing through the TSV.
To verify the accuracy of the proposed model, the quantitative values of the via parasitics are validated against the experimental results provided by Savidis et al. [33], who extracted electromagnetic solutions for the resistance and inductance for a Cu-based cylindrical-shaped TSV using a three-dimensional (3D) numerical simulation tool. For verification of the closed-form expression, the quantitative values of the via resistance and inductance are calculated at the given technology in Ref. [33] and compared with the simulated data in Fig. 3a and b, respectively.
To enable a comparison with the experimental results, values of the TSV diameter (d tsv ) in the range from 5 to 60 µm are considered, with aspect ratios of 0.5, 1, 3, 5, 7, and 9. The via resistance and inductance are calculated at an operating frequency of 2 GHz and shown in Fig. 3. Good agreement is observed between the experimental results and the calculated values of the resistance and inductance. The maximum difference between the analytical and experimental values of the TSV resistance and inductance is only 8.02% and 4.95%, respectively.

The CNT-based TSV model
This subsection presents the equivalent electrical model and the techniques used to calculate the parasitics for the TSVs based on the SWCNT then MWCNT bundles. The modeling of the via parasitics primarily depends on the number of conducting channels in each SWCNT present in a bundle. The total number of SWCNTs (N CNT ) in a bundle is calculated using the radius of each SWCNT (r CNT ), the radius of the TSV (r via ), and the van der Waals distance ( ≈ 0.34 nm) between adjacent SWCNTs. N CNT can be represented as The number of conducting channels in a MWCNT is a function of the shell diameter [34]. All the SWCNTs in a bundle have either metallic or semiconductor nature depending on their chirality, whereas MWCNTs are always metallic. For the metallic SWCNTs in a bundle, the average number of conducting channels for an SWCNT of a particular diameter is where D i is the diameter of the ith shell of the MWCNT (or SWCNT) and k 1 and k 2 takes values of 2.04 × 10 −4 nm −1 and 0.425, respectively. The quantitative value of d t is determined from the thermal energy of the electrons and the gap between the two subbands, which is equivalent to 1300 nm.k at T = 300 K. For D i > 4.3 nm, the average number of conducting channels is proportional to the shell diameter. Therefore, the total number of conducting channels in a bundle can be calculated by taking the sum of the conducting channel of each SWCNT as The conduction mechanism in a CNT is ballistic due to the long mean free path (mfp) in the range of micrometers. The diameter following mfp can be expressed as Thus, the total number of conducting channels can be expressed as The electrical equivalent RLGC model of the CNT bundlebased TSV considering the eddy resistance is shown in Fig. 4. Each CNT in a bundle contributes broadly three types of resistance: (1) the scattering resistance ( r ∕ bundle ) that occurs due to the fact that the nanotube is longer than the mfp of the electron, (2) the quantum resistance ( R q ) due to the quantum confinement of the electrons and depending on the N channel of each SWCNT/ MWCNT in a bundle, and (3) the resistance corresponding to the imperfect contact between the metal and the nanotube ( R mc ) with an approximate value of 3.2 kΩ , arising 3 The parasitic parameters of the C-TSV at an operating frequency of 2 GHz: a the resistance and b the inductance due to the fabrication process [34][35][36][37]. Thus, the equivalent scattering and quantum resistances can be expressed as where h and e denote Planck's constant and the electron charge, respectively. The equivalent RLGC model of the CNT bundle includes two types of capacitance: (1) the quantum capacitance ( c ∕ q_bundle ) arising due to the finite electronic states in a quantum wire and (2) the electrostatic capacitance ( c ∕ E_bundle ) that is due to the potential difference between the CNT bundle and the ground plane. c ∕ q_bundle and c ∕ E_bundle in p.u.h. can be expressed as The resistances due to the eddy current induced by the changing electromagnetic field are the same as those for the Cu TSV described above. Equations (1)-(31) are used for the calculation of the parasitic parameters of the C-TSVs based on copper or the CNT bundles. Furthermore, the values obtained for the parasitic parameters Fig. 4 An equivalent RLGC circuit model of the CNT-based C-TSV with consideration of the eddy effect when considering TSVs based on Cu or CNT bundles are summarized in Table 2 for different via heights and operating frequencies. Note that the quantitative values of the parasitic parameters are smaller for the MWCNT bundles compared with the the Cu TSV, irrespective of the via height. As shown in Table 2, the eddy resistance in the neighboring TSV R e_tsv has a great impact at high frequencies due to the eddy effect and the skin effect. Table 2 The values of the parasitic parameters for the C-TSVs based on Cu and the SWCNT or MWCNT bundles for different via heights and operating frequencies

Performance analysis
This section illustrates the impact of the eddy current on the crosstalk-induced delay, peak noise, and power dissipation using the RLGC model proposed for the TSV at the 7-nm technology node. A three-line DVL setup (Fig. 5) is used for the circuit-level simulations of the TSV with 20 distributed pi networks using industry-standard software (Synopsys HSPICE version 2020). Each via line represents the RLGC model of the TSV as shown in Figs. 2 and 4. The vias are driven by a field-effect transistor (FET) instead of a complementary metal-oxide-semiconductor (CMOS) driver at the 7-nm technology node. However, several challenges are introduced when scaling down the technology, such as the closer proximity of the TSVs and the ultrahigh-resolution lithography requirements. With an increase in the TSV density, the impact of the cross-coupling capacitance becomes more severe and isolating them from one another becomes a challenging task. As a result, the performance of the overall system degrades [38]. On the other hand, the physical dimensions at lower technology node require a complex, costly fabrication process and require ultrahigh-resolution lithography [39]. Although CMOS performs well down to the 28-nm technology node, below this it shrinks in such a way that short channel-effects become uncontrollable. As a result, the gate is unable to control the leakage path. In the case of a FET driver, good control of the gate on the leakage path is obtained at lower technology node, hence FETs can be used as suitable drivers. In Fig. 5, each via line is terminated with a load capacitor C load of 200 aF. Using the setup illustrated in Fig. 5, the subsequent sections analyze the overall reliability of the TSV in terms of the crosstalkinduced delay, peak voltage, and power dissipation for different operating frequencies and via heights.

The crosstalk delay analysis
This subsection presents an analysis of the crosstalk-induced delay of the C-TSV with consideration of the eddy effect in terms of the dynamic crosstalk delay, applying the DVL setup shown in Fig. 5. The transmission line introduces some delay when the signal passes through it. In this situation, one of the transmission lines can act as an aggressor while the other can act as a victim. The dynamic crosstalk delay phenomena is introduced when all the signals provided to the aggressor and victim lines are in the same or the opposite switching state at the same time. However, in the case of outof-phase crosstalk delay, all the signals exhibit the opposite switching transition from each other [40]. Furthermore, this out-of-phase crosstalk delay represents the worst case due to the higher Miller capacitive factor (MCF) between the vias [25]. Hence, this work considers the opposite switching transition state in the calculation of the crosstalk delay, e.g., where the aggressor line switches from high to low and the victim from low to high. Figure 6 shows the crosstalk delay of the TSVs based on Cu and the SWCNT or and MWCNT bundles, obtained with and without consideration of the eddy effect, for different via heights and frequencies.
From Fig. 6, it is clear that the delay for the TSV based on MWCNT bundles is considerably lower in comparison with those based on the SWCNT bundle or Cu. The primary reason underlying this finding is that the quantitative values of the coupling capacitance of the MWCNT bundle are lower as compared with the other via designs. Note also that the delay with the eddy effect is substantially higher than that without considering the eddy effect. This occurs  due to the fact that the impact of the eddy current is greater at high frequencies, revealing that the eddy resistance in the neighboring TSV R e_tsv rises with frequency, as also seen in Table 2. Additionally, it can also be observed that the crosstalk-induced delay increases with the TSV height and the operating frequency. This occurs due to the higher values of the parasitics as the via height or frequency is increased, as also shown in Table 2.
Additionally, Fig. 7 presents the rate of change in the crosstalk delay for different frequencies with respect to the delay obtained at 20 GHz. This percentage change for the TSVs based on Cu and the SWCNT and MWCNT bundles with and without consideration of the eddy effect for a via height of 120 nm is shown in Fig. 7. Note that the percentage change in the delay is greater at higher frequencies due to the corresponding increase in the delay. However, the rate of change of the crosstalk delay without consideration of the eddy effect is more severe than the variation in the delay when including the eddy effect. The percentage difference in the crosstalk delay when comparing the results obtained with versus without consideration of the eddy effect is 21.14%, 31.63%, 35.77%, and 38.35% at a frequency of 120, 200, 300, and 500 GHz, respectively, for the Cu-based TSV. Similarly, these differences in the delay for the TSV based on SWCNT bundles are 15.57%, 16.12%, 26.18%, and 27.04%, respectively, while the differences in the delay for the TSV based on the MWCNT bundle are 1.66%, 18.08%, 21.17%, and 25.29%, respectively. It can be observed that this difference in the rate of change in the delay improves when considering the TSV based on the MWCNT bundles. The average percentage change in the delay when including the eddy effect is 31.73%, 21.23%, and 16.55% for the TSVs based on Cu and the SWCNT and MWCNT bundles, respectively.
The percentage increment in the crosstalk-induced delay of the C-TSV at the 5-nm technology node with respect to the 7-nm technology is presented in Table 3 for various frequencies. It has been observed that the delay without the eddy effect increases on average by 3.4 times for Cu but only 2.6 times for the MWCNT-bundle-based TSV. However, the increment in the delay when including the eddy effect is reduced to 1.4 times for Cu, whereas for the MWCNTbundle-based TSVs it is encouragingly reduced to 0.9 times. Therefore, it can be concluded that the MWCNT-bundlebased TSV demonstrates an improved delay compared with Cu at lower technology nodes.

Peak noise
This subsection discusses the impact of the eddy effect on the peak noise of the TSV. Conceptually, noise coupling takes place in the region of the substrate whenever fast signal transition occurs within the TSV. This coupling mechanism is similar to the noise coupling that takes place into the substrate through the source/drain junctions of a transistor. However, due to the greater dielectric area, the dielectric capacitance of the TSV is larger than the source/ drain junction capacitance. TSV-related substrate noise coupling is therefore one of the primary noise injection  mechanisms in 3D integrated circuits [41]. Peak noise is observed when the aggressor line is supplied with an inphase signal while the victim line is grounded. This results in the formation of unintentional peaks that are observed on the victim line, which is responsible for faults in digital circuits [42]. Figure 8 shows the peak noise voltage of the TSVs based on Cu and SWCNT or MWCNT bundles, with and without consideration of the eddy effect, for different TSV heights and frequencies. From Fig. 8, it can be observed that the peak noise voltage in the TSV based on MWCNT bundles is lesser as compared with those based on the SWCNT bundles or Cu due to the reduced coupling factor. Note also that the peak noise when including the eddy effect is considerably lower than that without considering it. Additionally, the peak noise is greater for higher TSVs and operating frequencies. The reason behind this finding is the higher parasitic values, which increase with the height and frequency as observed from Table 2.
Additionally, Fig. 9 shows the rate of change in the peak noise voltage for different frequencies with respect to the delay obtained at 20 GHz. This percentage change is calculated for the TSVs based on Cu and SWCNT or MWCNT bundles, with and without consideration of the eddy effect, at h tsv = 120 nm, as shown in Fig. 9. Note that the percentage change in the noise voltage is considerably greater at higher frequencies due to the rise in the noise voltage with increasing frequency. However, the rate of change of the noise voltage when considering the eddy effect is more severe than without its consideration. The percentage difference in the peak noise voltage when calculated with versus without consideration of the eddy effect is 3.38%, 2.83%, 2.65%, and 2.45% at frequencies of 120, 200, 300, and 500 GHz, respectively, for the Cu-based TSV. Similarly, these differences in the peak noise voltage for the TSV based on SWCNT bundles are 3.04%, 2.64%, 2.61%, and 2.32%, while those for the TSV based on MWCNT bundles are 2.84%, 2.59%, 2.24%, and 2.05%, respectively. Note that the difference in the rate of change of the noise voltage improves when using the TSV based on MWCNT bundles. The average percentage change in the noise voltage when including the eddy effect is 2.83%, 2.65%, and 2.45% for the TSVs based on Cu and the SWCNT MWCNT bundles, respectively.

The power dissipation analysis
This subsection demonstrates the impact of the eddy resistance on the dynamic power dissipation. The power dissipation is obtained by providing an in-phase signal either from low to high or from high to low through the coupled TSVs. Figure 10 shows the power dissipation of the TSVs based on Cu and the SWCNT or MWCNT bundles obtained with and without consideration of the eddy effect for different TSV heights and frequencies. Note that the TSVs based on   Fig. 9 The percentage change in the peak noise of the TSVs based on a Cu, b SWCNT bundles, and c MWCNT bundles for different frequencies with respect to that obtained at 20 GHz, with and without considering the eddy effect, at h TSV = 120 nm MWCNT bundles but without the eddy resistance dissipate the least power among all the filler materials, as shown in Fig. 10. Additionally, the power consumption increases for higher TSVs and operating frequencies. The reason behind this finding is the higher quantitative values of the parasitics, which increase for higher TSVs and frequencies as seen in Table 2.
Furthermore, Fig. 11 presents the rate of change of the power dissipation for different frequencies with respect to that obtained at 20 GHz for a TSV height of 120 nm. This percentage change is calculated for the TSVs based on SWCNT and MWCNT bundles, with and without consideration of the eddy effect, as shown in Fig. 11. It is seen that the percentage change in the power dissipation is greater at higher frequencies. However, the rate of change of the power dissipation when considering the eddy effect is more severe than without its consideration. The percentage differences in the power dissipation when obtained with versus without consideration of the eddy effect is 0.17%, 0.43%, 0.6%, and 0.77% at frequencies of 120, 200, 300, and 500 GHz, respectively, for the Cu-based TSV. Similarly, these differences in the power dissipation are 0.08%, 0.35%, 0.52%, and 0.69%, respectively, for the TSV based on the SWCNT bundles, and 0.18%, 0.25%, 0.34%, and 0.31%, respectively, for the TSVs based on MWCNT bundles. Note that this difference in the rate of change of the power dissipation improves when using the TSV based on MWCNT bundles. The average percentage change in the power dissipation when including the eddy effect is 0.4925%, 0.41%, and 0.27% for the TSVs based on Cu and SWCNT or MWCNT bundles, respectively.
The percentage reduction in the peak noise voltage and the dynamic power dissipation of the C-TSV at the 5-nm technology node with respect to the 7-nm technology node is summarized in Tables 4 and 5, respectively, at various frequencies. Note that the peak noise and dynamic power dissipation without consideration of the eddy effect are reduce by approximately 7.24% and 35.2%, respectively, for the Cu-based TSV. In contrast, for the TSV based on the MWCNT bundles, it is reduced by 7.54% and 37.69%, respectively. However, the reduction in the peak noise voltage and dynamic power dissipation when including the eddy effect is 7.96% and 35.4%, respectively, for the Cu-based TSV, whereas for the TSV based on MWCNT bundles, it is encouragingly 8.24% and 37.79%, respectively. It can thus be concluded that the TSV based on MWCNT bundles demonstrates improved peak noise and dynamic power dissipation characteristics compared with Cu at this smaller technology node.    Fig. 11 The percentage change in the power dissipation of the TSVs based on a Cu, b SWCNT bundles, and c MWCNT bundles at different frequencies with respect to that obtained at 20 GHz, with and without consideration of the eddy effect, at h TSV = 120 nm To analyze the static power dissipation of the TSV at the Deep Sub Micron (DSM) level, results for the 10-nm, 7-nm, and 5-nm technology nodes are shown in Fig. 12. Note that the static power dissipation increases as the technology is scaled down because of an increase in the leakage current I leakage [43], as shown in Eq. (32).
where V DD is the supply voltage to the TSV and I leakage is the leakage current due to movement of charge carriers from the TSV to the silicon substrate. Furthermore, the liner and depletion layers are used to isolate the TSV to reduce the leakage current. However, the thicknesses of the liner and depletion layers are reduced when scaling down the technology, as revealed by Table 1. Hence, the leakage current increases substantially at smaller technology nodes. It can thus be concluded that an increase in the leakage current is a primary challenge when scaling down such technology.
(32) P static = I leakage × V DD , Table 4 The percentage reduction in the peak noise at the 5-nm technology node with respect to the 7-nm technology node at different frequencies Frequency (GHz) The percentage (%) decrease in the peak noise for the 5-nm technology node with respect to the 7-nm technology node

Conclusions
A novel pi-type equivalent RLGC model for TSVs based on Cu and SWCNT or MWCNT bundles and considering the eddy effect at high frequencies at the 7-nm technology node is proposed herein. A closed-form expression for the eddy resistance is derived for the depletion region and the substrate and in the neighboring TSV. Furthermore, the performance of the TSV is analyzed in terms of the crosstalk delay, peak noise, and power dissipation with consideration of the eddy effect at high frequencies. The results reveal that the impact of the high-frequency eddy current is substantially lesser in the case of the TSV based on MWCNT bundles as compared with those based on Cu or SWCNT bundles. The overall difference is approximately 16.55%, 2.45%, and 0.27% for the crosstalk delay, noise voltage, and power dissipation, respectively.