Analysis of Eddy Effect for Cu and CNT Bundle Based Through-Silicon Vias: Impact on Crosstalk and Power

The performance of a three dimensional integrated circuit primarily depends on the filler material used in through silicon via (TSV). The mostly used filler material Cu is primarily facing severe reliability issues due to the skin effect and electromugration related problems at high frequencies. Therefore, in recent, single- and multi-walled carbon nanotubes (SWCNT and MWCNT) have been emerged as suitable filler materials in TSV. Additionally, at high frequencies, an electrmagetic force primarly induces to an eddy current that adversely affects the overall performance of a TSV. This paper for the first time demonstrates the impact of eddy current on Cu, bundled SWCNT and MWCNT based TSVs. An accurate RLGC circuit model is proposed by considering the eddy effect at the depletion layer and the silicon substrate region. The equivalent circuit parameters are modelled at 7 nm technology using a three line driver-via-load setup. Using the proposed setup, crosstalk and power disspation are analyzed with and without considering the eddy effect. Irrespective of TSV heights, the MWCNT bundle demonstrates substantially lower crosstalk delay, peak noise and power dissipation in comparison to the Cu and SWCNT bundle based TSVs.

In the recent past, several researchers have contributed in designing Three Dimensional (3D) integrated circuits (ICs) as an alternative solution to conventional 2D planar ICs, wherein IC layers are stacked vertically to integrate more devices on a single chip ensuring improved performance [1][2][3]. This process, referred to as 3D stacking, primarily results in higher transistor density, lower power dissipation, enhanced speed, and reduced footprint area. For interconnection purposes in 3D IC, Through Silicon Via (TSV) is mainly used that provides higher density and bandwidth, low latency, and provides homogeneous and heterogeneous integration [4]. The performance of 3D IC is primarily dependent on the type of filler material used in TSV [5]. Mostly, copper (Cu) is used as filler material in the TSV due to its higher conductive nature and is comparatively compatible in via last TSV fabrication process. In addition to this, Cu provides good thermal cycling performance, lesser stress, void-free filling, conductivity, and higher current density than tungsten and polymer [6]. However, challenges due to fabrication limitations in accomplishing Physical Vapour Deposition (PVD) and Seed Layer Deposition are observed in Cu-based TSVs. Therefore, researchers are compelled to find an alternative solution to replace the Cu TSVs. Carbon Nanotubes (CNTs) have emerged as the most promising filler material as an alternative choice to Cu. The CNTs are hollow cylindrical-shaped structures made up of concentrically rolled-up graphene sheets at a specific angle [7]. Two types of CNTs auch as single-(SWCNT) and multi-walled CNT (MWCNT) are generally preferred as filler materials. Negligible electromigration, thermal stability, unique electrical and mechanical properties provide CNT an edge over other materials to be considered suitable as TSV filler [8]. Thus compared to Cu TSV, impressive results can be observed in CNT-based TSV.
At high frequencies, eddy resistance primarily plays a key role for modelling of a TSV using Cu and CNT as filler materials. As per Faraday's law of induction, the magnitude of induced electromotive force (EMF) is directly proportional to the rate of change of magnetic flux [9]. Thus induced EMF can work on the other conducting material of the TSV, and an eddy current will generate in it. According to the Lenz's law, the eddy current opposes the change of magnetic field that is the main reason behind its circulatory nature [10]. Thus eddy resistance comes into the existence in the silicon substrate, neighboring TSVs, and depletion regions due to the flow of eddy current. In general, most of the state-ofthe art experimental evidences [11][12][13][14][15][16][17][18][19][20] describes an equivalent RLGC model of the cylindrical-shaped TSV without considering the eddy effect at high frequencies.
Previously, Khalil et al. [11] demonstrated an analytical model of Cu-based TSV that depends on its physical parameters. The researchers studied the propagation delay of the TSV by using a transmission line model and electromagnetic field solver using both structural and analytical simulation by neglecting the impact of highfrequency eddy current. Afterward, Xu et al. [12] presented a comparative study of propagation delay of TSV with different filler materials like Cu, SWCNT, and MWCNT bundle. In the proposed circuit model, the authors have considered eddy resistance in the silicon substrate. However, the impact of the eddy effect in the depletion layer and neighboring TSVs were ignored. Later, Kim et al. [13] presented a compact ac model of the TSV including the via bump, redistribution layers, and skin effect. On the other hand, their frequency-based measurement techniques alongwith several other physical parameters such as inter-metal dielectric (IMD) layer, bump, and underfilled layer were considered for the analysis. The analysis was based on an eye diagram that demonstrates signal amplitude for different frequencies using the method described in [14]. However, the impact of the eddy effect is ignored in the TSV modeling in the case of high frequencies. Researchers in [15] proposed a comprehensive model of SWCNT bundle-based TSV to represent a driver-via-load (DVL) setup that presents significant improvement in delay and power performance with an increase in aspect ratio, although it was ignored in high-frequency analysis. Subsequently, Qian et al. [16] proposed a lumped crosstalk noise model to capture TSV to TSV coupling noise in CNT-based 3D IC but neglected the impact of eddy resistance at the higher frequency. Later, Su et al. [17] proposed an equivalent model of MWCNT based TSV using temperature effects that considered the eddy resistance due to the flow of eddy current in the substrate but neglected the eddy resistance impact due to depletion region and TSV material. Lu et al. [18] demonstrated a pi equivalent electrical model of the Cu-based cylindrical TSV with consideration of eddy current and proximity effect at high frequencies. However, the authors restricted their research related to the impact of the eddy effect only for the S parameter that shows the power loss of the TSV. Later, Liao et al. [19] demonstrated the crosstalk-induced delay considering the proximity effect in a shielded pair of the TSV. The proposed model provides a good agreement with the analytical calculations and 3D fullwave simulation. Although a comprehensive analysis has been performed for transmission coefficient and high-frequency impedance considering TSV design parameters but the impact of the eddy effect is restricted only to the silicon substrate. In recent, the researchers in [20] have demonstrated the crosstalk induced delay and power dissipation for cylindrical, tapered, square, and annular shaped TSVs considering the skin effect at high frequency. The authors proposed an electrical equivalent model of metal-insulator-semiconductor (MIS) and metalsemiconductor (MES) based on different TSV shapes to analyze the power delay product (PDP). The analysis is majorly focused on the TSV shapes and at high frequencies. However, the impact of several design parameters such as mutual inductance, eddy resistance, and depletion capacitance were ignored. Therefore, the state-of-the-art research [11][12][13][14][15][16][17][18][19][20] fails on some fronts to present a comprehensive analysis of eddy current for a pair of TSV at high frequencies, and hence a detailed investigation is required to apostrophize the eddy resistance of TSVs by considering all the physical parameters.
This research work for the first time demonstrates the electrical modeling of the TSV considering the eddy effect at high frequencies. Whenever high-frequency alternating current passes through the TSV, it causes the varying electromagnetic field that generates an induced EMF in the other conducting layers such as depletion region, silicon substrate, and the neighboring TSVs. Due to the induced EMF, a circulatory current known as eddy current primarily flows in it. Thus, an eddy resistance comes to an existance due to the flow of eddy current at high frequencies. Hence, all these phenomena are normally known as the eddy effect. In order to demonstrate this effect, a closed-form expression of the eddy resistance is derived for the depletion region, silicon substrate, and neighboring TSVs. In addition, Metal Oxide Semiconductor (MOS) effect is also considered during the RLGC modeling of the TSV. Furthermore, the liner and the depletion layers are used to provide isolation to the TSV from the silicon substrate. Similarly, Inter Metal Dielectric (IMD) and underfilled layers are used to isolate the bump from the silicon substrate and to prevent coupling between the bumps, respectively. This paper analyzes the crosstalk and power performance using a three line parallel DVL, wherein the via line is modelled with Cu, SWCNT, and MWCNT bundles as filler materials. The model primarily considers the impact of eddy effect at 7 nm technology [21]. The main reason behind choosing a 7 nm technology node is that it provides higher device density, improved power-saving, and better performance. A unique 20 distributed pi type network is used for the electrical circuit model. Due to the performance accuracy, the pi type distributed network is considered instead of L-and T-type networks [22][23].
The paper is organized in the following sections: Section 1 sheds light on the recent state-of-art research scenario and briefs the modeling of cylindrical-shaped TSV taking into account the impact of eddy resistance. Section 2 introduces the electrical equivalent model of Cu, SWCNT, and MWCNT (number of shells n = 10) bundle-based TSV with and without consideration of eddy resistance. A detailed analytical expression is derived to model the eddy resistance in the silicon substrate, depletion region, and neighboring TSVs. Based on the proposed model, Section 3 demonstrates a comprehensive study of the impact of eddy resistance in the crosstalk noise, delay, and power dissipation concerning different heights and frequencies. Finally, Section 4 briefly concludes this work with a summary.

TSV Model and Eddy Resistance
This section demonstrates a cylindrical-shaped TSV structure and their physical parameters using different filler materials such as Cu, SWCNT and MWCNT bundle. Furthermore, a closed-form expression of eddy resistance is derived for the depletion region, silicon substrate, and in the neighboring TSVs. Consequently, a novel equivalent electrical modeling of cylindrical TSV is proposed with consideration of the eddy resistance.

TSV Structure and Physical Parameters
This subsection gives a detailed insight of the TSV structure and quantitative values of several parameters that will eventually be used in the modeling of equivalent RLGC model. Figures 1(a) and 1(b) shows the physical configuration and top cross-sectional view of cylindrical TSV, respectively. The TSV is surrounded by an insulating layer such as liner (usually SiO2) and depletion layers to provide the DC isolation and prevent leakage between TSV and the substrate. Usually, copper is used as a filler material in TSV and the bump. A cylindrical-shaped pillar bump is used to provide a contact to the TSVs with a different functional block of the dies. In general, an IMD and underfilled layer is used to isolate the bump from the substrate and reduce the cross-coupling between the bumps, respectively. Lossy silicon material is considered as a substrate, whereas the depletion region consists of the lossless silicon to reduce the leakage. Silica-filled anhydride resin polymers are used in the underfilled layer to prevent coupling between the bumps.
The physical parameters of the cylindrical TSV is designed at 7 nm technology [24] as shown in Fig. 1. Under the proposed TSV model, the via pitch i.e. center-to-center distance between adjacent TSVs (pvia) is considered as 23 nm. TSV pitch (pvia) should be equal to or greater than twice the TSV diameter (dtsv) to avoid the misalignment [25]. Based on this concept, the diameter (dtsv) is approximated as 10.5 nm. The height (htsv) of TSV is taken in the range of 30-120 nms. Considering an aspect ratio of 2.4, the height (hbump) and diameter (dbump) of the bump are approximated as 3.71 nm and 22.26 nm, respectively. The thickness of oxide liner (tliner) and depletion width (tdep) are approximated as 1.05 nm and 1.65 nm, respectively [12]. The height of the IMD layer (hIMD) is 1.05 nm. The number of CNT bundles in a TSV is calculated using the cross-sectional area of TSV and diameter of CNTs in a bundle.

Cu based TSV Model
This subsection demonstrates the Cu-based TSV modeling with consideration of the eddy effect in the silicon substrate, depletion region, and neighboring TSVs. Firstly, a closed-form expression of eddy resistance in the silicon substrate is derived by using the physical dimension of the TSV as shown in Fig.  1. The equivalent RLGC circuit model of the 3-line TSV at high frequency is presented in Fig. 2 varying magnetic field. Thus, magnetic vector potential ⃗⃗ is calculated by using the Maxwell equation [26][27] as

 
where σSi,eff = σSi+jωμεsi is the effective conductivity of the silicon substrate and ω is the angular frequency. Assuming the magnetic vector potential has only z directional component and it varies in radial direction r of the TSV, the variation in the ϕ and z will be zero in the cylindrical coordinate system. Therefore, ∂Az/∂z = 0, ∂Az/∂ϕ = 0. In this way, the simplified Eqn. (1) can be expressed as where ks= (-jωμSiσSi,eff) 1/2 . Using the solution of the Bessel function, Eqn.
(2) can be simplified as where c1 and c2 are the arbitrary constant, a1=rTSV+tliner+tdep and b1= [pvia-(rTSV+tliner+tdep)]. It is assumed that the total current I is passing through the TSV. Hence, the Ampere's law can be used to obtain the magnetic vector potential in the depletion and insulating layers as where rTSV ≤ r ≤ a1 or b1≤ r≤ (pvia-rTSV) Applying the boundary condition in the TSV as Eqn.
Now, c1 and c2 can be obtained after solving the above expressions as and Electric current density in the substrate is Jz sub (r) that can be derived from Eqn. (3), (9), and (10) Hence, the eddy resistance in the substrate ( _ ′ ) can be obtained by using Eqn. (13) and that can be expressed in per where h = htsv-2×hIMD for the calculation of eddy resistance over the total height. In the same way, eddy resistance in the depletion region ( As shown in the Fig. 2, rest of the other parasitic parameters of the TSV can be obtained by using the TSV physical dimensions. First of all, the total capacitance (Cuimd) is a parallel combination of underfilled (Cuf) and IMD capacitances (Cimd). The Cuf exists between the bump pairs due to the presence of underfilled layer that is made of silica-filled anhydride resin polymer. However, Cimd exhibits between the TSV pairs due to the presence of IMD layer [28]. The Cuf and Cimd can be modeled as parallel-wire capacitance [13]. (17) A silicon substrate capacitance ( ′ ) is formed between the TSVs due to the presence of conductive silicon substrate. The ′ can be derived using the parallel-wire capacitance model [29] where height is considered as h = htsv-2×hIMD. In addition to this, substrate conductance ′ exists between the TSV pairs due to the presence of lossy characteristics of the silicon substrate. The ′ can be obtained by using a relationship between the ′ and ′ as discussed in [13]. Liner capacitance ′ exists between the TSV and depletion layer due to the presence of the oxide layer [13]. In addition to this, depletion capacitance ′ formed between the TSVs surrounded by the oxide layer and the Si substrate in the presence of the depletion layer [29].
Apart from this, the total resistance of the circuit ′ in Fig. 2 is a series combination of the TSV resistance ′ and the bump resistance ′ .  (20) where ′ and ′ are obtained using the dc and ac components of the resistance in terms of p.u.h. Here, ac component of the resistance primarily considers the skin effect of the TSV [13]. On the other hand, the total inductance ′ is a series combination of bump inductance ′ and TSV inductance ′ [13]. Inductance forms due to the magnetic field that is produced by current passing through TSV.

CNT based TSV Model
This subsection presents the equivalent electrical model with the parasitic calculation techniques for SWCNT bundle, followed by MWCNT bundle based TSVs. The modeling of via parasitic primarily depends on the number of conducting channels in each SWCNT present in a bundle. The total number of SWCNTs (NCNT) in a bundle is calculated using the radius of each SWCNT (rCNT), the radius of TSV (rvia), and the Vander Waals distance ( ≈0.34) between the adjacent SWCNTs. The NCNT can be represented as The number of conducting channels in MWCNT is a function of the shell diameter [30]. All the SWCNTs in a bundle act as either metallic or semiconductor based on their chirality whereas MWCNTs are always metallic. For metallic SWCNT in a bundle, the average number of conducting channels for a particular diameter of SWCNT is as follows where represents the diameter of the ith shell of MWCNT (or SWCNT) and 1 2 possess a value of 2.04 × 10 −4 −1 and 0.425, respectively. The quantitative value of is determined from the thermal energy of electrons and the gap between the two sub-bands that is equivalent to 1300 nm.k at T=300K. For > 4.3 nm, the average number of conducting channels is proportional to its shell diameter. Therefore, the total number of conducting channels in a bundle can be calculated by taking the summation of conducting channel of each SWCNT as The conduction mechanism of CNT is ballistic due to the long mean free path (mfp) in the range of micrometers. The diameter following mfp can be expressed as: Thus, the total number of conducting channels can be expressed as The electrical equivalent RLGC model of CNT bundle-based TSV considers the eddy resistance as shown in Fig. 3. Each CNT in a bundle comprises of broadly three types of resistances: (1) scattering resistance ( / ) that occurs due to higher nanotube length exceeding mfps of the electron, (2) quantum resistance ( ) due to the quantum confinement of electron and depends on the ℎ of each SWCNT/ MWCNT in a bundle, and (3) imperfect metal-nanotube contact resistance ( ) with the approximated value of 3.2 kΩ arising due to the fabrication process [30][31][32][33]. Thus, the equivalent scattering and quantum resistances can be expressed as where h and e represents the plank's constant and electronic charge, respectively.  , and / = 2 ln ( ).   The resistances due to eddy current induced by changing electromagnetic field are the same as that of Cu TSV. Equations (1) to (31) are used for the calculation of the parasitic parameters of the copper and CNT bundlebased cylindrical TSVs. Furthermore, the parasitic parameter values with different TSV heights and operating frequencies are summarized in Table 1 for Cu and CNT bundle-based TSVs. It is observed that the quantitative values of the parasitic parameters are lesser for MWCNT bundle compared to the Cu TSV irrespective of via height. As shown in Table 1, the eddy resistance in the neighboring TSV Re_tsv becomes more effective at high frequencies due to the eddy effect and skin effect.

Performance Analysis
This section illustrates the impact of eddy current on the  Fig. 4) is used for circuit-level simulation of the TSV with 20 distributed pi networks. Each via line represents the RLGC model of the TSV as shown in Fig. 3. The vias are driven by a field effect transistor (FET) instead of CMOS driver at the 7nm technology node. Although a CMOS performs well up to 28 nm technology but below 28 nm technology, CMOS shrinks in such a way that the short channel effect becomes uncontrollable. As a result, the gate is unable to control the leakage path. In the case of FET driver, there is good control of the gate on the leakage path at the lower technology and hence FET is used as a suitable driver. In Fig. 4, each via line is terminated with the load capacitor Cload = 200aF. Using the above mentioned setup in Fig. 4, the subsequent sections have analyzed the overall reliability of the TSV in terms of crosstalk induced delay, peak voltage, and power dissipation for different operating frequencies and via heights.

Crosstalk Delay Analysis
This subsection presents the crosstalk induced delay analysis of cylindrical TSV with consideration of the eddy effect in terms of dynamic crosstalk delay by using the DVL setup as shown in Fig. 4. The transmission line experiences some delay at the same time as the signal passes through it. In this situation, one of the transmission lines can act as an aggressor and the other can act like a victim. Dynamic crosstalk delay phenomena is introduced when all signals provided to the aggressor and victim lines are in the same or the opposite switching state at the same time. However, in the case of out-phase crosstalk delay, all signals are in the opposite switching transition from each other [34]. Furthermore, out-phase crosstalk delay is the worst-case delay due to a higher Miller Capacitive Factor (MCF) between the vias [23]. Hence, this work considers the opposite switching transition state for crosstalk delay calculation such as aggressor line switches from high to low and victim is low to high. Figure 5 shows the crosstalk delay of Cu, SWCNT, and MWCNT bundle based TSVs that are obtained with and without consideration of eddy effect for different via heights and frequencies. From Fig. 5, it is clear that the delay of MWCNT bundle based TSV is considerably lower in comparison to the SWCNT bundle and Cu-based TSVs. The primary reason behind this is that the quantitative values of the coupling capacitance of the MWCNT bundle are lower as compared to other vias. It can also be noticed that the delay with eddy effect is substantially higher than the delay without considering the eddy effect. It is due to the fact that the impact of eddy current is more effective at high frequencies that shows the eddy resistance in neighboring TSV Re_tsv rises with frequencies as observed from Table 1. Additionally, it can be also observed that the crosstalk induced delay increases with the TSV heights and operating frequencies. It is due to the higher values of parasitics that increases for more via height and frequencies as witnessed from Table 1.
Additionally, Fig. 6 presents the rate of change in crosstalk delay for different frequencies w.r.t. the delay obtained at 20GHz. This percentage change is obtained for Cu, bundled SWCNT and MWCNT based TSVs with and without

Frequency (in GHz)
Cu without eddy effect Cu with eddy effect SWCNT without eddy effect SWCNT with eddy effect MWCNT with eddy effect MWCNT with eddy effect consideration of eddy effect at 120 nm TSV height as shown in Fig. 6 It can be noticed that the percentage change in delay is more for higher frequencies due to a rise in the delay for an increasing frequency. However, the rate of change of crosstalk delay without considering the eddy effect is more server than variation in the delay including the eddy effect. The differences in the percentage of crosstalk delay with and without considering the eddy effect are 21

Peak Noise
This sub-section discusses the impact of eddy effect on peak noise of the TSV. Conceptually, noise coupling takes place in the region of substrate whenever a fast signal transition happens within the TSV. This coupling mechanism is similar to the noise coupling taking place into the substrate through source/drain junctions of a transistor. However, due to the greater dielectric area, the dielectric capacitance of a TSV is larger than source/drain junction capacitance. TSV related substrate noise coupling is therefore one of the primary noise injection mechanisms in 3D integrated circuits [35]. Peak noise is observed when the aggressor line is supplied with the in-phase signals and the victim line is grounded. It results in the form of unintentional peaks observed at the victim line which is responsible for faults in digital circuits [36]. Figure 7 demonstrates the peak noise voltage of Cu, SWCNT and MWCNT bundle based TSVs with and without consideration of eddy effect for different TSV heights and frequencies. From  Fig. 7, it can be observed that the peak noise voltage in MWCNT bundle based TSV is lesser as compared to SWCNT bundle and Cu-based TSVs due to the less coupling factor. It can also be noticed that the peak noise with eddy effect is considerably lower than the peak noise without considering eddy. Additionally, the peak noise is more for higher TSVs and operating frequencies. The reason behind this is the higher parasitic values that increases with the height and frequencies  Additionally, Fig. 8 demonstrates the rate of change in peak noise voltage for different frequencies w.r.t. the delay obtained at 20 GHz. This percentage change is calculated for Cu, SWCNT bundle and MWCNT bundle based TSVs with and without consideration of eddy effect at htsv = 120 nm as shown in Fig. 8. It is observed that the percentage change in noise voltage is considerably higher for more frequencies due to a rise in the noise voltage with an increase in frequencies. However, the rate of change of noise voltage considering the eddy effect is more server than without the eddy. The differences in the percentage of peak noise voltage with and without considering the eddy effect are 3.38%, 2.83%, 2.65%, and 2.45% at 120GHz, 200GHz, 300GHz, and 500GHz frequencies, respectively for Cu based TSV. Similarly, these differences in peak noise voltage for bundled SWCNT-based TSVs are 3.04%, 2.64%, 2.61%, and 2.32% at 120 GHz, 200 GHz, 300 GHz, and 500 GHz frequencies, respectively. The differences in peak noise voltage for bundled MWCNT based TSVs are 2.84%, 2.59%, 2.24%, and 2.05% at 120 GHz, 200 GHz, 300 GHz, and 500 GHz frequencies, respectively. It can be noticed that this difference in the rate of change of noise voltage is improving when moving towards the MWCNT bundle based TSV. The average percentage change in the noise voltage w.r.t. eddy effect is 2.83%, 2.65%, and 2.45% for Cu, SWCNT bundle and MWCNT bundle based TSVs, respectively.

Power Dissipation Analysis
This sub-section demonstrates the impact of eddy resistance on dynamic power dissipation. The power dissipation is obtained by providing the in-phase signal either from low to high or high to low through the coupled TSVs. Figure 9 shows the power dissipation of Cu, bundled SWCNT and MWCNT based TSVs that are obtained with and without consideration of eddy effect for different TSV heights and frequencies. It has been observed that the bundled MWCNT without eddy resistance dissipates the least power among all filler materials as shown in Fig. 9. Additionally, the power consumption rises for higher TSVs and operating frequencies. The reason behind this is the higher quantitative values of parasitics that increases for higher TSVs and frequencies as witnessed in Table 1. At h TSV = 120 nm Frequency (in GHz) % change in power dissipation w.r.t. 20 GHz MWCNT w/o eddy effect MWCNT with eddy effect calculated for SWCNT and MWCNT bundle based TSVs with and without consideration of the eddy effect that is shown in Fig 10. It can be illustrated that the percentage change in power dissipation is more for an increase in frequencies. However, the rate of change of power dissipation considering the eddy effect is more severe than variation in the power dissipation without the eddy effect. The differences in the percentage of power dissipation with and without considering the eddy effect are 0.17%, 0.43%, 0.6%, and 0.77% at 120 GHz, 200 GHz, 300 GHz, and 500 GHz frequencies, respectively for Cu based TSV. Similarly, these differences in power dissipation for SWCNT bundle based TSVs are 0.08%, 0.35%, 0.52%, and 0.69% at 120 GHz, 200 GHz, 300 GHz, and 500 GHz frequencies, respectively. The differences in power dissipation for MWCNT bundle based TSVs are 0.18%, 0.25%, 0.34%, and 0.31% at 120 GHz, 200 GHz, 300 GHz, and 500 GHz frequencies, respectively. It can be observed that this difference in the rate of change of power dissipation is improving when moving towards the MWCNT bundle based TSV. The average percentage change in power dissipation w.r.t. eddy effect is 0.4925%, 0.41%, and 0.27% for Cu, SWCNT, and MWCNT bundle based TSVs, respectively.

Conclusion
This paper proposed a novel pi type equivalent RLGC model of Cu, SWCNT and MWCNT bundle based TSVs considering the eddy effect at high frequencies at 7 nm technology. A closed form expression of eddy resistance is derived for depletion region, substrate and in the neighboring TSV. Further, the performance of the TSV is analyzed in terms of crosstalk delay, peak noise and power dissipation of the TSV with concern of the eddy effect at high frequency. It has been observed that the impact of high frequency eddy current is substantially lower in case of MWCNT bundle based TSV as compared to the Cu and SWCNT bundle. The overall differences are approximately 16.55%, 2.45% and 0.27% in terms of crosstalk delay, noise voltage and power dissipation, respectively.  An equivalent RLGC circuit model of the CNT based C-TSV considering eddy effect Figure 4 Driver-Via-Load (DVL) setup for circuit-level simulation Figure 5 Crosstalk delay of Cu, SWCNT and MWCNT bundle based TSV at via heights of (a) hTSV=30 μm, (b) hTSV=60 μm, (c) hTSV=90 μm and (d) hTSV=120 μm  Peak noise of Cu, SWCNT and MWCNT bundle based TSV at via heights of (a) hTSV=30 μm, (b) hTSV=60 μm, (c) hTSV=90 μm and (d) hTSV=120 μm Power dissipation of Cu, SWCNT and MWCNT bundle based TSV at via heights of (a) hTSV=30 μm, (b) hTSV=60 μm, (c) hTSV=90 μm and (d) hTSV=120 μm Percentage change in power dissipation of (a) Cu, (b) SWCNT bundle and (c) MWCNT bundle for different frequencies w.r.t. the power obtained at 20 GHz with and without considering the eddy effect at hTSV = 120 nm.