An Approach for Drain Current Modeling Including Quantum Mechanical Effects for a DMDG Junctionless Field Effect Nanowire Transistor

This paper presents the effects of quantum confinements on the surface potential, threshold voltage, drain current, transconductance, and drain conductance of a Dual Material Double Gate Junctionless Field Effect Nanowire Transistor (DMDG-JLFENT). The carrier energy quantization on the threshold voltage of a DMDG-JLFENT is modeled, and subsequently, other parameters like drain current were analytically presented. The QME considered here is obtained under the quantum confinement condition for an ultra-thin channel, i.e., below 10 nm of Si thickness. The threshold voltage shift due to QME can be used as a quantum correction term for compact modeling of junctionless transistors. The analytical model proposed for surface potential, threshold voltage, drain current, transconductance, and drain conductance were verified by TCAD 3-D quantum simulation results which makes it suitable for SPICE compact modeling.


Introduction
As the IC industry moves toward very low dimensions of the order of 10 nm and below the need for alternate device structure are highly desirable. To overcome the fabrication difficulty to maintain very steep junctions at low dimensions, recently, an alternate MOS structure named Junctionless transistor was proposed [1]. Several analytical models were developed for double gate junctionless transistor with symmetric gate, assymetric gates [2][3][4][5][6][7]. The quantum confinements models are also available in literature for these structures [8][9][10]. Even though this structure has many advantages the leakage current in the sub-threshold regime of Double Gate Junctionless Field Effect Transistors (DG JLFET) is considerably high. It flows through the center of the channel i.e., volume conduction occurs due to the low concentration of the depletion charge carriers [11,12]. The necessity for materials with high work function (~5.6 eV) arises from turning the device properly OFF and lowering the subthreshold leakage current [13], which is technologically challenging. To overcome this problem, the use of dual material (DM) in the gate [1,4] was suggested, enhancing the electrostatic performance of the device by incorporating a step in the surface potential profile.
In 2014, Agarwal et al. [13] proposed a pseudo-2-D surface potential model for dual material double gate junctionless field-effect transistor (DMDG-JLFET). Baruah et al. [14] presented a study on analog circuit performance of a DMDG-JLFET with a high k-spacer. Recently, Kumari et al. [11] proposed a theoretical investigation of DMDG-JLFET for analog and digital performance. Gupta et al. [15], showed that a continuous increase in the threshold voltage was observed as we move down towards sub 10 nm regime of the silicon film thickness. The growth is less prominent above 10 nm silicon thickness which occurs due to QMEs [16]. Because of the high substrate doping and ultra-thin silicon thickness, severe band bending on the substrate occurs. The narrowing of potential well in the interface is sufficient for energy quantization of the carrier [17]. As a result, the inversion charge density will get reduced at the same gate bias compared to the classical mechanically computed results. The inclusion of quantum mechanical analysis becomes necessary when the device dimensions are scaled down to 10 nm as the QME governs the device performances at such a small dimension. This paper has included the QME on DMDG JLFENT by incorporating the shift in threshold voltage and charge quantization effects. The analytical model results were verified with that obtained from the 3-D GENIUS Visual TCAD quantum simulation, which shows the high accuracy of our model.

Analytical Model
The 3-D Poisson's equation in the channel region for the DMDG JLFENT device shown in Fig. 1(a), can be written as where, ψ(x, y, z) = Potential at any point in the channel, N si = Channel doping concentration, ε si = Dielectric constant of silicon, V = Quasi-Fermi potential, V T = Thermal voltage, As the variation along the width (z) is very less so we consider a parabolic potential profile as where ψ s (x)is the surface potential, α(x), β(x)are arbitrary coefficients that are functions of 'x'. The total channel length is L = 20 nm and L M1 = 10 nm, L M2 = 10 nm is the portion of the channel under the metal M 1 and M 2, respectively.

Surface Potential Model
In DMDG JLFENT we have two different gate materials with different work functions so the flat-band voltages can be given as here φ M1 , φ M2 are work functions of metal M 1 , M 2 and φ si is that of the silicon region, respectively. Now, the potential under the gate (M 1 ) can be written as, Similarly, the potential under the gate (M 2 ) can be written as, The Poisson's eq. (1) under two gates can be solved using the boundary conditions: 1. The electric flux at the front gate-oxide interface is continuous, here, the gate oxide capacitance is C ox ¼ ε ox t ox f ¼b ð Þ , where ε ox is the dielectric constant of the oxide layer and t ox(f = b) is symmetric oxide layer thickness i.e. both front and back oxide thickness are considered to be same. Moreover, we have used high-k material HfO 2 as a gate oxide which gives better results compared to SiO 2 in ultra scaled transistors [18].

2.
The surface potential at the interface of two different materials is continuous, 3. The electric field at the interface of two different materials is continuous, Considering the extra depletion 'd S ' into the source region, we have the potential at the source end to be, The potential at the drain end similarly can be given as, In junctionless transistor's high current flows before the flat band condition, we would consider full and partial depletion modes of operations that are enough for most practical applications. Poisson's equation neglecting mobile charge in depletion mode (V GS < V Th ) can thus be written as, due to symmetry, the electric field at the center is zero thus The coefficients α j1 (x), β j2 (x)can be obtained from the (6), (7), and (13) where j = 1, 2. Using the values of coefficients in (4) and (5) and then substituting the potentials in (12) we have, When V Th < V GS < V FB , the transistor operates in partial depletion mode during which a neutral region starts to develop in the middle of the device. Taking the origin to be at the center of the device, the electric field and depletion thickness 'y d ' can be calculated as [13], where, The potential in the neutral region follows a simple parabolic potential approximation [19], where the potential at the center (V C ) of the device can be approximated as, The coefficients α j1 (x), β j2 (x)are deduced from the boundary conditions (8), (9), and (18). Substituting their corresponding values in (4) and (5) and then from (12), we obtain, where,

Combination of Operating Modes
As the gate work functions are different (ϕ M1 > ϕ M1 ), thus the threshold and the flatband voltages for the gate under metal M 1 (G M1 ) are higher than that of the gate under metal M 2 (G M2 ). When we apply gate voltage, the corresponding channel region may be in different modes of operations. The first useful combination is the full depletion under G M1 and partial depletion under G M2. Under this condition, the surface potentials are, where the coefficients are deduced using the boundary conditions eqs. (6)(7)(8)(9). Similarly, the surface potential for the second possible combination, i.e., channel region under both the gates G M1 and G M2 , is in partial depletion. It happens when gate voltage crosses the threshold voltage of G M1 .

Threshold Voltage Model
Substituting y d = −t si /2 in eq. (17) and solving for the gate voltage, we get the threshold voltage as,

Inclusion of Quantum Mechanical Effect
In the subthreshold region of junctionless transistors, the channel is fully depleted, the channel potential is bent, and electrons are preferentially confined at the center of the channel. The Schrödinger's equation can be decoupled from the Poisson's equation by neglecting the mobile charge term in the Poisson's equation, when t si is large the discrete subband energy is mostly confined between the bent portion of the conduction band boundaries. In this case, the system is similar to a quantum harmonic oscillator (QHO) with an energy potential given as [17], Using the effective-mass approximation, the discrete subband energy levels can be expressed as where n is a quantum number (n = 0, 1, 2, 3...), and h is the Planck's constant. When the t si is small, the discrete sub-band energy levels for this case are expressed by [17].
where, k = 1 and 2; n = 1,2,3….. The quantum shift in threshold voltage is incorporated by the energy quantization of the carriers in a channel. In a silicon crystal with <100> orientation, six valleys in the conduction band clustered into two separate groups with degeneracy factors g 1 = 2 and g 2 = 4, respectively [20].
Quantum Shift in threshold voltage can then be expressed as [20], where, The threshold voltage including the quantum shift now can be expressed as Thus surface potential becomes The eq. (28) gives the surface potential with QME. However, it can be noted that while carrying out investigations, the QME is assumed to be uniform throughout the channel.

Drain Current and Transconductance Model
The drain current equation for DMDG JLFENT, including the quantum effect, can be obtained by using (27) for threshold voltage in linear and saturation regions of operations as where, κ = μ n C ox (W/L).. The gate transconductance equation is obtained from (30) as The drain conductance equation is obtained from (29) as

Results and Discussion
To validate the semi-analytical model for threshold voltage, drain current, and transconductance, the results were compared with that obtained from GENIUS 3-D TCAD software [21]. Figure 1  hence subject to surface roughness and scattering which are absent in the junctionless transistor as volume current conduction occurs. Throughout the paper the oxide thickness is considered to be 2 nm unless mentioned. The GENIUS VTCAD 3D quantum simulation results are shown as symbols, and the thick lines represent the results obtained from our analytical model for all results illustrated in this paper. Figure 2-3, shows the surface potential variations with V GS for two different values of silicon thickness of 10 nm and 6 nm, respectively. In both the figures, we can observe a step increase in the surface potential due to the use of two dissimilar metals having different work functions. As the work function increases, the surface potential decreases; thus the surface potential under the gate G M1 is lower than that of the gate G M2 . Figure 2, where silicon thickness is 10 nm, shows the surface potential bent is more prominent under the gate G M1 due to higher work function difference, thereby controlling the threshold voltage, therefore the name control gate. When V GS is 0 V, the bent is highest and the region under G M1 is fully depleted and under G M2 is partially depleted. As the V GS increases the bent decreases and at 0.6 V the region under G M1 is partially depleted and under G M2 is near flat band. In fig. 3, the silicon thickness is considered 6 nm; the bent is more prominent than that of 10 nm at any given V GS, which can be explained based on higher QME or confinement effect with a decrease in silicon thickness. The quantum effect is more prominent since the electron concentration peaks below the silicon-oxide interface and goes nearly zero at the interface, which is entirely in contrast to the classical model. Classically, the electron concentration peaks at the surface. The bending that occurred in the curve at the end portion is due to the inclusion of d S (depletion towards source region) and d D (depletion towards drain region) in our analytical model. In both cases the model shows excellent agreement with that of the quantum simulation results of 3-D VTCAD software. Figure 4, shows the surface potential variations along the channel for different values of silicon thickness from 4 nm to10nm, while V DS kept at 0.5 V and V GS kept at 0.4 V, respectively. Here we can observe that as the silicon thickness decreases from 10 nm down towards 4 nm, the bent in the surface potential contours also increases and this happens because of a higher control of gate over the channel, and the charge carriers become more and more confined due to higher QME.
The transfer characteristics of the DMDG JLFENT were plotted in Fig. 5-7. The variation of the drain current to the gate voltage is shown in Fig. 5. While V DS was kept constant, the silicon thickness was varied from 10 nm down to 4 nm.
Here we can observe that, as silicon thickness decreases, the drain current reduces for the same value of V GS . Moreover, we can observe that at 4 nm, the curve is not smooth because of distortion that occurred due to the high confinement effect or QME. Figure 6, shows the same plot on a semi-logarithmic scale, reflecting the low leakage current in smaller silicon body thickness due to better control of the gate over the channel. Figure 7, shows the variation of the drain current regarding V DS where V GS was kept constant at 0.5 V and silicon thicknesses are being varied. Here we can note that as silicon thickness decreases, the drain current reduces, which is evident for reduced charged carriers and confinement effects. In all the cases Fig. 5-7, the model is in good agreement with quantum simulation results of 3-D VTCAD software.
The transconductance for varying silicon thickness model was plotted in Fig. 8; we can observe that the plot for T si of 4 nm is low up to the threshold voltage and increases just after crossing it. This may be because of the very high confinement effect as compared to others. Figure 9, shows the drain conductance model for various silicon thicknesses where we can observe that the conductance was low for lower dimensions owing to lower corresponding drain currents. In both cases,

Summary
This paper investigated the effects of quantum confinements on the several key parameters of a DMDG-JLFENT. The carrier energy quantization on the threshold voltage of a DMDG-JLFENT is analytically modeled. The QME considered here is obtained under the quantum confinement condition for an ultrathin channel, i.e., below 10 nm of Si thickness. Based on the shifts in threshold voltage, the change in drain current, transconductance, and drain conductance with quantum effects were modeled. The analytical model proposed for surface potential, threshold voltage, drain current, transconductance, and drain conductance were verified by GENIUS Cogenda VTCAD 3-D quantum simulation results. The model is thereby suitable for compact modelling.
Acknowledgments The author is highly thankful to the Dr. R. Subadar, HOD, Department of Electronics and Communication Engineering, NEHU Shillong for providing the software support in carrying out this work.
Author Contribution All work carried out by the author N. bora.

Funding
The authors did not receive support from any organization for the submitted work.
• No funding was received to assist with the preparation of this manuscript.
• No funding was received for conducting this study.
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