Analog/RF Performance of Triple Material Gate Stack-Graded Channel Double Gate-Junctionless Strained-silicon MOSFET with Fixed Charges

In this paper, analog/radio frequency (RF) electrical characteristics of triple material gate stack-graded channel double gate-Junctionless (TMGS-GCDG-JL) strained-Si (s-Si) MOSFET with fixed charge density is analyzed with the help of Sentaurus TCAD. By varying the various device parameters, the analog/RF performance of the proposed TMGS-GCDG-JL s-Si MOSFET is evaluated in terms of transconductance-generation-factor (TGF), early voltage, voltage gain, unity-power-gain frequency (fmax), unity-current-gain frequency (ft), and gain-transconductance frequency product (GTFP). The results confirm that the proposed TMGS-GCDG-JL s-Si MOSFET has superior analog/RF performance compared to gate stack-graded channel double gate-junctionless (GS-GCDG-JL) s-Si device. However, the proposed MOSFET has less transconductance and less output conductance when compared with the GS-GCDG-JL s-Si device in above threshold region, and reverse trend follows in sub-threshold region.


Introduction
Nano scaled strained-silicon (s-Si) MOSFETs are promising candidates for upcoming high-speed devices on account of high field velocity, enhanced mobility, and higher driving current [1][2][3][4][5][6]. With the aid of layer transfer process [7], the strain is developed in the silicon material. In this method, the biaxial-tensile strain is introduced in silicon material by growing the silicon material on the relaxed Si (1−X) Ge (X) material, which is developed on the Silicon-on-insulator (SOI) layer. When device operates in nano-scaled regime, fixed charges are created at Oxide/s-Si (SiO 2 /s-Si) interface due to the lateral electric field in s-Si MOSFETs [8,9]. Thereby, the performance of MOSFET deteriorates in terms of threshold voltage and channel potential.
A few authors have presented the impact of fixed charges on the electrical characteristics of double gate (DG) junctionless device [10][11][12]. Also, they have confirmed that the fixed charges at the SiO 2 /s-Si interface of MOSFET can cause change in the channel potential and threshold voltage. To suppress the hot carrier effects (HCEs), the triple metal gate (TMG) engineering is introduced in DG MOSFET [13,14]. In TMG structure, screen and control gates are used with three distinct work functions. Therefore, a step equivalent profile in s-Si channel potential and increase in average electric-field of s-Si channel are obtained. Hence, the performance of DG device is improved by employing the TMG structure. To further suppress HCEs, gate stack (GS) structure is also incorporated in DG MOSFET to achieve better device performance in terms of gate leakage current and drive current [15,16]. Furthermore, graded channel (GC) engineering is employed in DG junctionless device, thus resulting in improved analog/RF characteristics owing to diminished HCEs [17,18]. Therefore, better performance of the DG junctionless MOSFET is obtained by employing the GS with gate and channel engineering.
The analog/RF electrical characteristics of junctionless MOSFETs for low power applications was demonstrated in [19]. Moreover, enhancement in early voltage and intrinsic voltage gain are attained due to low electric field at drain end of oxide interface. In [20], the effect of laterally graded channel doping in double gate junctionless MOSFETs for analog/RF applications was presented. Besides, high cutoff frequency and high intrinsic voltage gain are obtained. In [21], the comparative analysis of DG junction less and GS DG junction less MOSFETs was presented. Also, the effect of doping on obtaining the optimum performance of the device was studied. In [22], the analytical modeling of leakage currents in dual material halo doped cylindrical gate junctionless MOSFET was illustrated. Till now, in literature, the analog/RF characteristics of triple material gate stackgraded channel DG-junctionless (TMGS-GCDG-JL) s-Si device with the fixed charges has not been presented. By employing the GC and GS structure with gate engineering, better analog/RF performance of junctionless s-Si DG device is achieved. In the sub-nano scaled dimensions, the proposed device can be suitable for the RF-integrated circuit and 5G/6G communication applications due to its low values of power consumption and gate capacitance, high intrinsic gain, high unity current gain frequency and large band-width.
The process flow of a proposed MOSFET as follows, firstly, the strained-Si channel is fabricated with help of hydrogen-induced and wafer bonding material transfer of strained-Si grown on bulk relaxed SiGe graded layers [7]. In the next step, GC region is achieved with the help of diffusion process by using three mask layers. Next, bottom and top gate stacks are formed by develop of the oxide material by dry thermal oxidation process at modest temperatures and deposition of triple metal gates such as screening and control gates are deposited by normal and tilt angle evaporation method, respectively. In the next step, the bottom and top gate stacks are etched and patterned, followed by drain and source areas are formed by diffusion process with activation energy at very high temperatures. Lastly, the electrodes for gate, drain, and source are created at high temperatures.
This paper demonstrates the analysis of analog/RF characteristics of TMGS-GCDG-JL s-Si device with fixed charges. The analog/RF characteristics of TMGS-GCDG-JL s-Si device is exhaustively analyzed by varying the strain (m), fixed charge density (N f ), and the thickness of high-k material (t ox2 ). Moreover, the analog figure of merits of the proposed MOSFET are evaluated in terms of transconductance generation factor T GF = g m I ds , early voltage I ds g ds , and intrinsic voltage gain g m g d . Besides, the RF figure of merits of the proposed device, unity current gain frequency (f t ), unity power gain frequency (f max ) and gain transconductance frequency product  GT F P = g m g d g m I d f t , are evaluated exhaustively. The analog/RF characteristics of the proposed junctionless s-Si device are improved by increasing in the t ox2 , m, and positive N f in the below threshold region, and vice-versa in above threshold voltage region. Also, better analog/RF electrical characteristics of the proposed TMGS-GCDG-JL s-Si MOSFET are obtained when compared to GS graded channel DG junctionless (GS-GCDG-JL) s-Si MOSFET.

Proposed MOSFET Structure and TCAD Setup
The simulated cross sectional view of TMGS-GCDG-JL s-Si device with fixed charges is demonstrated in Fig. 1(a). The strained-silicon graded channel region is doped with three different uniform phosphorous doping concentrations (i.e., N d1 , N d2 , and N d3 ). Screen and control gates are used together to form bottom and top gates of TMGS-GCDG-JL s-Si device. The bottom and top gates of the GS-GCDG-JL s-Si MOSFET has a single gate layer whose work function is an average of φ m1 , φ m2 and φ m3 . Because of HCEs in nano scaled proposed s-Si junctionless MOSFET, interface charges are created at s-Si/SiO 2 interface and are represented as damaged region of length L d , as demonstrated in Fig. 1(a). The drain current of s-Si MOSFET is calibrated with the transfer characteristics of the strained-silicon MOSFET using TCAD [23], as shown in Fig. 1(b). It is obvious from Fig. 1(b) that the TCAD simulation results of strained-silicon MOSFET are in good accordance with the experimental results shown in [23]. The various parameters and dimensions of the proposed TMGS-GCDG-JL s-Si MOSFET are used in the simulation are listed in Table 1.
Since the strain is developed into silicon channel, the energy-band diagram of the silicon material is affected because of the biaxial-tension. Thereby, energy band gap of silicon and effective mass of the carriers decrease, whereas electron affinity (χ Si ) increases. The changes in energy band gap, electron affinity, and effective masses of carrier in s-Si material are formulated as shown below [24,25] (ΔE c ) s−Si = 0.57X, where V T denotes the thermal voltage, N V ,Si and N V ,s−Si represent density of states in the valence band, m * h,Si and m * h,s−Si denote the effective masses of hole in silicon and strained-silicon, respectively. Also, both flat band voltage and barrier potential of the source (drain) to channel decrease simultaneously [26].
where ΔV f b and ΔV bi are the changes in flat band voltage and built-in potential, respectively. The proposed device with the fixed charges is simulated using the TCAD [27]. In the device simulation, to evaluate the analog/RF characteristics of the TMGS-GCDG-JL s-Si deice with fixed charges, the following physical models are considered. The charge transport mechanism is estimated with the help of the drift diffusion model and the recombination of carriers are determined by using Auger and SRH recombination models. And also, mobility of carriers is estimated by using Enormal mobility model and high field saturation model. Moreover, the energy band gap narrowing effects are considered by the OldSlotboom model and strained-silicon characteristics are assessed by MoleFraction model. Furthermore, the effect of fixed Ge mole fraction m 0.1 -0. 3 10 Fixed charges N f −4 × 10 12 -4×10 12 cm −2

Result Analysis
This section demonstrates the analog and radio frequency performance of the TMGS-GCDG-JL s-Si MOSFET with fixed charges using the simulation results obtained from TCAD. Figure  The variation of t ox2 on g m and transfer characteristics of TMGS-GCDG-JL s-Si MOSFET is shown in Fig. 3. When t ox2 decreases, increment in both g m and transfer characteristics of MOSFET are observed in the above threshold region because of the greater gate control over the s-Si channel than drain and reverse trend follows in weak inversion region. Besides, the gate stack that consists of HfO 2 in the TMGS-GCDG-JL s-Si MOSFET has better g m and transfer characteristics than the gate stack that consists of Si 3 N 4 in the above threshold region and inversely in subthreshold region.
The variation of N f with L d on the transfer characteristics and g m of the proposed TMGS-GCDG-JL s-Si MOSFET is depicted in Fig. 4. The enhanced transfer characteristics of the TMGS-GCDG-JL s-Si device are attained by increasing positive N f since the threshold voltage of device decreases, and reverse trend follows for the negative N f . Moreover, as positive/negative fixed charge density increases, the transconductance of TMGS-GCDG-JL s-Si MOSFET increases in sub-threshold region and reverse trend follows in strong inversion region. Hence, the analog/RF characteristics of the proposed TMGS-GCDG-JL s-Si MOSFET are affected with respect to the fixed charges at SiO 2 /s-Si interface. Figure 5 depicts the variation of m on the output characteristics and g d of TMGS-GCDG-JL s-Si MOSFET. As strain increases, better drain characteristics and high g d of the TMGS-GCDG-JL s-Si MOSFET are attained because of decrease in the threshold voltage of proposed The variation of t ox2 on output characteristics and g d of the TMGS-GCDG-JL s-Si MOSFET is illustrated in Fig. 6. As t ox2 decreases, g d decreases and the proposed MOSFET achieves better drain characteristics. Besides, the gate stack that consists of HfO 2 in the TMGS-GCDG-JL s-Si MOSFET has improved drive current and less g d than the gate stack that consists of Si 3 N 4 . Therefore, HfO 2 /SiO 2 gate stack of proposed TMGS-GCDG-JL s-Si has better electrical characteristics and less impact of V ds on the channel when compared to the Si 3 N 4 /SiO 2 gate stack, as shown in Fig. 6. The variation of strain on TGF and intrinsic gain of TMGS-GCDG-JL s-Si is depicted in Fig. 8. As strain increases in the TMGS-GCDG-JL s-Si MOSFET, TGF decreases and intrinsic voltage gain increases owing to increasing the values of transconductance and drain current of the proposed device, as depicts in Fig. 2. When compared to GS-GCDG-JL s-Si device, TMGS-GCDG-JL s-Si device has better TGF and higher g m g d due to high g m and low g d of the TMGS-GCDG-JL s-Si device, as illustrated in Figs. 2 and 5. Thereby, the proposed device has higher analog voltage gain and superior power efficiency due to TMG structure when compared to GS-GCDG-JL s-Si device. Figure 9 plots the effect of t ox2 on the voltage gain and TGF of the TMGS-GCDG-JL s-Si MOSFET. The power conversion efficiency and voltage gain of proposed MOSFET decrease because of the less gate control over the strained-Si channel than drain terminal as t ox2 increases. Moreover, gate stack with HfO 2 has better TGF and higher voltage gain than the gate stack with Si 3 N 4 of the TMGS-GCDG-JL s-Si MOSFET due to the higher g m and lower g d of the TMGS-GCDG-JL s-Si MOSFET, as illustrated in   Figs. 3 and 6. Therefore, the proposed MOSFET with Si 3 N 4 has higher analog intrinsic gain and low power consumption are obtained.
The effect of N f on the intrinsic voltage gain and TGF of the TMGS-GCDG-JL s-Si device is shown in Fig. 10. As positive N f increases, TGF decreases and intrinsic voltage gain increases owing to the decrease in threshold voltage of TMGS-GCDG-JL s-Si MOSFET, and vice-versa for negative fixed charge density. Hence, the TMGS-GCDG-JL s-Si MOSFET with negative fixed charge density can be operated at lower bias values, and vice-versa for positive N f . Moreover, the proposed MOSFET with positive N f has higher analog intrinsic gain is attained. Figure 11 shows the variations of m and t ox2 on the early voltage of TMGS-GCDG-JL s-Si device. The early voltage of the TMGS-GCDG-JL s-Si MOSFET increases as m increases and t ox2 decreases since the g d of the device decreases, as illustrated in Figs. 5 and 6 (low early voltage denotes the high channel length modulation effect in the MOSFET). Besides, gate stack with HfO 2 has greater early voltage than the gate stack with Si 3 N 4 of the TMGS-GCDG-JL s-Si MOSFET since the output conductance for gate stack with HfO 2 is less, as depicts in Fig. 6. Moreover, the proposed TMGS-GCDG-JL s-Si MOSFET has higher early voltage than the GS-GCDG-JL s-Si MOSFET due to the less output conductance of the proposed device, as depicts in Fig. 5. As a result, the effect of channel length modulation in proposed TMGS-GCDG-JL s-Si MOSFET is less compared to the GS-GCDG-JL s-Si MOSFET. Figure 12 demonstrates the effect of N f on early voltage of the TMGS-GCDG-JL s-Si MOSFET. The early voltage of the proposed device decreases/increases by increasing the negative/positive fixed charge density due to a increment/decrement in the output conductance with respect to negative/positive N f , as demonstrated in Fig. 7. Hence, effect of channel length modulation in the device increases/decreases due to negative/positive fixed N f at s-Si/oxide interface. Figure 13 demonstrates the effect of m on f t and total gate capacitance of the TMGS-GCDG-JL s-Si MOSFET. As m decreases, the f t and gate capacitance of the TMGS-GCDG-JL s-Si MOSFET decrease owing to an increment in the flat-band voltage of TMGS-GCDG-JL s-Si device and reduction of inversion carriers in strained-silicon channel. Moreover, when compared to proposed TMGS-GCDG-JL s-Si device, the gate capacitance and f t of the GS-GCDG-JL s-Si MOSFET are higher due to the higher g m of the GS-GCDG-JL s-Si device, as shown in Fig. 2.
The variation of t ox2 on the f t and gate capacitance of the TMGS-GCDG-JL s-Si device is depicted in Fig. 14. As t ox2 decreases, higher C gg and lower f t of the TMGS-GCDG-JL s-Si MOSFET are obtained due to the increase in inversion carriers in the channel. Besides, the gate stack with HfO 2 has higher gate capacitance than the gate stack with Si 3 N 4 of the TMGS-GCDG-JL s-Si MOSFET due to the higher permittivity of HfO 2 . However, the gate stack with HfO 2 has less f t than the gate stack with Si 3 N 4 of the TMGS-GCDG-JL s-Si MOSFET is noticed. Figure 15 shows the effect of fixed charged density on the gate capacitance and f t of the TMGS-GCDG-JL s-Si device. As negative N f increases, gate capacitance of the TMGS-GCDG-JL s-Si MOSFET decreases due to mitigate of inversion charges in channel of MOSFET, and reverse trend follows for positive N f . Moreover, as negative/positive N f increases, f t of the TMGS-GCDG-JL s-Si device decreases/increases because of the decrement/increment in g m of TMGS-GCDG-JL s-Si MOSFET with negative/positive N f , as demonstrated in Fig. 4. Figure 16 shows the variation of t ox2 on the voltage gain of the TMGS-GCDG-JL s-Si MOSFET with the operating frequency. As seen in Fig. 16, as t ox2 decreases, voltage gain of TMGS-GCDG-JL s-Si device increases because of decrement in g d and increment in g m , as shown in Figs. 2 and 5. Moreover, gate stack with HfO 2 has higher voltage gain than the gate stack with Si 3 N 4 of the TMGS-GCDG-JL s-Si MOSFET. However, as operating frequency increases, voltage gain of proposed MOSFET decreases owing to the more parasitic capacitive effects. Also, the proposed TMGS-GCDG-JL s-Si MOSFET has greater voltage gain than GS-GCDG-JL s-Si device because of the TMG structure in the proposed device. Figure Fig. 19. It is evident from    10 12 ≤ N f ≤ −2 × 10 12 , it is observed that GTFP of TMGS-GCDG-JL s-Si MOSFET increases/decreases as positive/negative interface charge density increases in the sub-threshold region and reverse trend follows in above threshold region. Besides, GTFP of the TMGS-GCDG-JL s-Si device reduces because of DIBL effect when N f > −2×10 12 . Hence, the overall analog/RF performance of the proposed the TMGS-GCDG-JL s-Si MOSFET varies with respect to fixed charges. The performance analysis of proposed TMGS-GCDG-JL s-Si MOSFET is compared with existing works in the previous works, as demonstrated in Table 2. The voltage gain, f t , and GTFP of proposed TMGS-GCDG-JL s-Si MOSFET (m=0.2 and t ox2 = 1nm) are better than when compared to the GS-GCDG-JL s-Si MOSFET (m=0.2 and t ox2 = 1nm), high-k spacer DG junctionless MOSFET [14], DG junctionless MOSFET with channel length 20 nm [19], GC DG junctionless device with channel length 30 nm [20] and strained-Si GC-DMDG MOSFET with channel length 20 nm [29] . However, the proposed TMGS-GCDG-JL s-Si MOSFET has lower early voltage than high-k spacer DG junctionless MOSFET [14]. Moreover, the proposed TMGS-GCDG-JL s-Si MOSFET has lower g m than strained-Si GC-DMDG MOSFET with channel length 20 nm [29]. Therefore, the proposed MOSFET using the TMG with GC engineering and gate stack techniques achieves improved overall analog/RF performance.

Conclusion
The analog/radio-frequency performance of the proposed TMGS-GCDG-JL s-Si MOSFET with fixed charge density at silicon dioxide interface has been estimated using TCAD tool. The proposed TMGS-GCDG-JL s-Si MOSFET has better overall analog/RF figure of merit compared to GS-GCDG-JL s-Si device in the above threshold region. Moreover, the analog/radio frequency figure of merits of TMGS-GCDG-JL s-Si device are improved by employing the TMG structure with the GC engineering and gate stack technique. An exhaustive analysis has been done to investigate the various analog/RF characteristics by varying MOSFET parameters of the TMGS-GCDG-JL s-Si MOSFET. Increments in TFP and GTFP of proposed TMGS-GCDG-JL s-Si MOSFET have been obtained by increasing values of strain, positive fixed charge density, and t ox2 in the weak inversion region, and vice-versa in the above threshold voltage region. Therefore, the proposed TMGS-GCDG-JL s-Si MOSFET has better analog/radiofrequency figure of merits in above the threshold voltage region.