An Energy Ecient Quantum-dot Cellular Automata Design of 1/2 and 1/3 Convolution Encoder

: Quantum-dot cellular automata (QCA) technology is considered to be the future of nanoelectronic device fabrication technology. The fabrication density of the transistors in a particular area in the current nanoelectronic industry has saturated. Adroit alternate to current CMOS based VLSI technology is being researched upon. QCA technology is considered to be the noblest post-CMOS era fabrication technology. In this paper, novel energy-efficient QCA designs for 1/2 and 1/3 convolution encoders have been presented. Both the presented designs were proven to be efficient than previously designed circuits. The efficiency of the design is calculated for critical design parameters like cell count, cell area, latency (clock phases), complexity and energy dissipation. The proposed 1/2 convolution encoder uses 21 QCA cells consuming an area of 0.012 µm 2 . The complexity of this design was calculated to be 2. The energy dissipation analysis revealed that the presented circuit dissipated 14.03 meV of energy. The proposed 1/3 convolution encoder uses 32 QCA cells consuming an area of 0.025 µm 2 . The energy dissipation analysis revealed that the presented circuit dissipated 16.88 meV of energy. Both the proposed designs used only a few more extra cells than the previously designed circuits but induced stronger polarizations and were more fault-tolerant. It was found that the circuits proposed are 25% more energy efficient than previously designed circuits. The latency of the proposed designs was of 2 clock phases, thus making it suitable for high-speed operation. Significant improvement of the designs was done to optimize the circuit for secure nano-communication devices.


Introduction
Quantum-dot cellular automata (QCA), the technology considered to be a potent contender for the post-CMOS (Complementary metal oxide semiconductor) era fabrication technology [2]. QCA technology due to its astonishing features like reversibility, ultra-low-power application and high-speed operation, has become a hot topic for research since the saturation of Moore's law in recent years. In QCA technology, the circuits are designed using quantum dots (quantum bits or quantum cells). In these quantum-dot based logic circuits, there is no actual flow of current. Instead, QCA cells inhabit and propagate polarizations based on the position of electrons in the quantum wells. The information is passed on and processed using polarization propagation to the neighbouring cells [3]. Reversibility is one of the focal features of QCA technology. A reversible QCA circuit has the potential to dissipate information processing energy less than the Shannon-Von Neumann-Landauer (SNL) limit of KBTln (2). These circuits can be used for ultra-low-power operation [4 -6]. Also, the QCA cells are of the size of 18x18µm 2 therefore, they enable high packaging densities during chip manufacturing.
Extensive research has been done to propose more and more efficient reversible gates, adders, flip flops and memory circuits. Only a trivial amount of research was done on topics related to communication engineering. Communication error check circuits like parity generators and detectors are some of the few circuits proposed in QCA technology [7,9]. Channel encoding and decoding is a vital component of digital communication setup. In channel encoding, the information bits being sent upon are encoded to a unique codeword. This helps in securing the communication and provides error-free communication in an inherent noisy channel. During channel encoding, the transmitting bit sequence is converted into an alternate bit sequence called a codeword. Redundancy is introduced during the convolution of the input sequence of bits. Linear block codes and convolution codes are the two types of channel codes. Convolution codes depend both on the present input sequence and the previously transmitted sequence. Thus, a need for memory element in CMOS logic implementation was compulsory. In this paper, a new energy-efficient and fault-tolerant design of the 1/2 and 1/3 convolution encoder is proposed.
In section 2 we have provided a brief introduction to the various building blocks of the QCA technology. In section 3 prior related work was discussed and in section 4 our proposed work was depicted and explained. In section 5 a state of art comparative analysis was drawn between the proposed designs and the previously proposed circuits.

QCA Background
Quantum-dot cellular automata is considered to be a potential substitute to the current CMOS based VLSI technology. This technique was first put forward by C. Lent and P.D. Tougaw in 1993 [2]. In quantum-dot cellular automata, the circuits are designed using quantum cells instead of conventional CMOS gate implementation [10]. These cells are square-shaped having four quantum wells separated by quantum barriers. Two of the opposite quantum wells have electrons residing in them. There are two ways in which the electrons can reside in quantum cells. Since only two possible diagonal positions are allowed, they result in two possible polarization (P). These two polarizations are used to depict two states in computation i.e., Logic 1 and Logic 0. The following subsections give an understanding of the basic concepts of QCA technology [11,12].

The QCA cell
Quantum-dots are arranged in unique ways to develop QCA designs. These quantum cells propagate the polarization instead of current like in current CMOS technology. The quantum cells work mainly on two fundamental concepts; the bi-stability of cell and the effect of the polarization of neighbouring cells. The electrons reside in the opposite quantum wells to minimize the coloumbic interaction. These electrons can only crossover to another set of quantum well only when supplied with enough tunnelling energy [3,11]. This tunnelling energy is called kink energy. The bistable nature of the quantum cells results in two possible polarizations representing two logic states (0 and 1). Fig. 1 shows the two states of the QCA cell. If electrons reside in quantum well 1 and 3, it is considered to be Logic 0 and polarization is said to be P = -1. On the other hand, if the electrons reside in quantum well 2 and 4, it is considered to be Logic 1 and the polarization is said to be P = +1 [13]. The polarization can be calculated from the following formula; Here, pi denotes the electronic charge at the i th quantum cell. The area between quantum wells stops the electrons from tunnelling from one quantum well to another and act as barriers. These barriers can only be overcome using sufficient clocking energy [14,15]. Based on the position of quantum wells in a QCA cell, it can be categorized into two types: 90 O cell and 45 O cell.

The 90 o Cell
In 90 O cells the quantum wells are situated at the four corners of the square cell. The electrons at all times reside in the diagonally opposite quantum wells to reduce the coulombic repulsion. It is the most commonly used QCA cell type used in designing logic circuits.

. The 45 o Cell
In a 45 O QCA cell, the quantum wells are located at the midpoints of the four sides of the quantum cell. This type of cell is also called a rotated QCA cell. In this type of QCA cell, the electrons are located on the opposite quantum wells. Fig. 3 shows a 45 O QCA cell.

Inter Cellular Interaction
The input at a particular cell is given by fixing the electron positions in two out of four quantum wells. The input cell then polarizes the cells surrounding it. Therefore, the data is propagated by the propagation of polarization. The electron interaction within a cell is given by; The influence on a particular cell under the influence of many other cells is given by the summation of the individual polarization influences of the cells surrounding it. It can be mathematically represented as; Here, and are the charges, ∈ is the relative permittivity, is the distance between the charges and ∈ o is the vacuum permittivity.

Clocking in QCA
The flow of information in QCA cell designs is regulated by the clocking. Meta-states in design are avoided using necessary power gain through clocking. Also, synchronization in the data flow can be maintained using clocking schemes. Quantum energy barriers between the quantum cells are managed using the QCA clock. Using the QCA clock the electrons are energized enough to tunnel to other quantum dots [14,15]. There are four phases to QCA clocking: 1. Switch Phase: During this phase, the energy barriers are raised thus the cells attain definite polarization. 2. Hold Phase: During the hold phase, the potential barriers are held at a higher value and proscribe electrons from tunnelling. The cells retain the polarization induced during the switch phase. 3. Release phase: During the release phase, lowering of the energy barriers starts and the electrons are released from their confinement in quantum wells. The cells lose their polarization during this phase. 4. Relax Phase: During the relax phase, the complete lowering of energy barriers takes place and electrons are completely free from confined quantum wells. This phase accounts for the meta-state of the cell. All these clocking phases have been depicted in Fig. 4.

Basic Building Blocks
There are two basic building blocks in QCA technology that are fundamental in designing the QCA layout for any given logic circuit. QCADesigner [16] simulation software is used to simulate the circuits.

Inverter:
NOT gate is the basic building block in developing any logic design. NOT gate simply inverts the input given to it. Fig. 5 depicts the QCA layout of the NOT gate. The output of the majority gate is simply what has more cardinality out of the three inputs. It can be simply modified to perform AND and OR logic function. Fig. 6

Prior Work
Quantum-dot cellular automata based 1/2 and 1/3 convolution encoders were previously designed in Ref [17], Ref [18] and Ref [19]. In Ref [17], Sen et al. presented a QCA design of 1/2 convolution encoder using 304 QCA cells consuming a cell area of 0.0984µm 2 . The total area consumed by the design was 0.497µm 2 . The latency incurred in this design was of 3 clock cycles or 12 clock phases. Also, a 1/3 convolution encoder was proposed in this paper which consumed 307 QCA cells. The cell area used by this design was 0.10µm 2 and the total area used was 0.697µm 2 . The latency incurred in this design was of 3 clock cycle or 12 clock phases. Both these designs were constructed using 12 majority gates and the complexity was calculated to be 18 for both the designs. No crossovers were used during designing of this circuit.
In Ref [18], Bahar et al. proposed efficient QCA designs of 1/2 and 1/3 convolution encoders. 30 cells were used in designing a 1/2 convolution encoder consuming a cell area of 0.021µm 2 and a total area of 0.021µm 2 . The latency incurred in this design was 0.5 clock cycle or 2 clock phases. The complexity of this design was calculated to be 2. Similarly, the design for 1/3 convolution encoder was constructed using 44 QCA cells consuming a cell area of 0.027µm 2 and a total area of 0.027µm 2 . The complexity of this design was calculated to be 3. No crossovers were used during designing of this circuit.
In Ref [19], Suhaib et al. proposed two different designs of 1/2 and 1/3 convolution encoder using two different techniques. For 1/2 convolution encoder, a cell count of 18 and 19 were used in the two different designs respectively. A total cell area consumption of 0.0058µm 2 and 0.0062µm 2 was used to propose two different designs. However, the latency of both the designs was 0.5 clock cycle or 2 clock phases. The two 1/3 convolution encoder designs were constructed using 30 and 40 QCA cells, consuming a cell area of 0.024µm 2 and 0.035µm 2 respectively. The latency incurred in both the designs was 0.5 clock cycle or 2 clock phases.

Proposed Work
The designs of the proposed 1/2 and 1/3 encoder with their corresponding simulation results are depicted in the below subsections respectively.

1/2 Convolution Encoder
The design for the presented 1/2 convolution encoder is proposed by cascading two 2-input XOR gates. The proposed design can be seen in Fig. 7 and the simulated waveform verifying its working is shown in Fig. 8.  Here, a0, a1 and a2 are the three inputs and the c0 and c1 are the two convoluted outputs. Using only 21 cells and consuming only 0.018µm 2 cell area this design is proposed. In this design, only 2 majority gates are used. A latency of two clock phases is incurred. There are no crossovers used in this design. The complexity of this design is calculated to be 2. Also, from the simulated waveform it can be concluded that the results obtained are in accordance with the desired outcomes and also within desired specifications.

1/3 Convolution Encoder
The design for the presented 1/3 convolution encoder is proposed by cascading three 2input XOR gates. The corresponding proposed design can be seen in Fig. 9 and the simulated waveform verifying its working is shown in Fig. 10.  Here, a0, a1, a2 and a3 are the four inputs and the c0, c1 and c2 are the three convoluted outputs. Using only 33 cells and consuming only 0.025µm 2 cell area this design is proposed. In this design, only 3 majority gates are used. A latency of three clock phases is incurred. There are no crossovers used in this design. The complexity of this design is calculated to be 3. Also, from the simulated waveform it can be concluded that the results obtained are in accordance with the desired outcomes and also within desired specifications.

Power Dissipation Analysis
Energy and Power dissipation plays a pivotal role in determining the efficiency of any circuitry. The energy and power dissipation analysis in QCA is done using the QCAPro tool [20]. QCAPro tool uses Coherence Vector analysis for accurate time-dependent dynamic simulation. Coherence Vector Engine is based on the density matrix approach. The coherence vector is a vector representation of the cell density matrix [3].
The first model for QCA that was power and energy considerate was developed by Lent. in Ref [21]. The first step in determining the power is to determine the two states of the QCA cell and that is calculated using the Hamiltonian matrix shown below [21,22]; Where, tells us about the polarization of the cell j. , is the Kink Energy between cell i and k. γ is the energy required for the electrons to tunnel within quantum cells. Then for each clock cycle, we need to calculate the QCA cell energy using eq. 2 [23]; Where ⃗ is the energy environment vector of a cell considering its neighbour's effect on it. ℏ is the Planks constant and ⃗ represents the coherent vector.
Only when the changing rate of ⃗ is maximum, maximum energy dissipation will occur [24]. Using equation 4 and 5 an approximate estimate of the energy and power dissipation can be easily calculated [25].
The energy dissipation maps for the proposed 1/2 and 1/3 convolution encoder are shown in Fig. 11 -16, for three levels of Kink Energy at a constant temperature, T = 2K. A comparative analysis based on the energy dissipation can be seen in table 1.

State of Art Comparative Analysis
For a 1/2 convolution encoder, the design proposed by Ref [17] consumed a cell area of 0.0697µm 2 . Then in Ref [18] the proposed convolution encoder drastically reduced the cell area to just 0.021µm 2 making an 85% increase in cell area efficiency. The design proposed in Ref [18] was however not fault-tolerant. In the design in Ref [19], the author proposed a faulttolerant circuit but this resulted in a compromise with energy dissipation.
For a 1/3 convolution encoder, the design proposed by Ref [17] consumed a cell area of 0.0697µm 2 . Then in Ref [18] the proposed convolution encoder drastically reduced the cell area to just 0.027µm 2 making an 80% increase in cell area efficiency. The design proposed in Ref [18] was however not fault-tolerant. In the design in Ref [19], the author proposed a faulttolerant circuit but this resulted in a compromise with energy dissipation.

Conclusion
In this paper, the energy-efficient QCA design of the 1/2 and 1/3 convolution encoder is presented. The proposed design of the 1/2 convolution encoder is constructed using 21 quantum cells. The reported cell count of previously designed circuits is in the range of 19 -304. But, due to various drawbacks like fault tolerance and high energy dissipation, these designs are not practically realizable. The proposed circuit is found to be 25% efficient in energy dissipation analysis. The proposed 1/3 convolution encoder is constructed using 32 quantum cells. The reported cell count of previously designed circuits is in the range of 30 -307. But, due to various drawbacks like fault tolerance and high energy dissipation, these designs are not practically realizable. The proposed circuit is found to be 30% efficient in energy dissipation analysis. Therefore, it can now be concluded that the proposed design while using only a few more cells is far more efficient on critical design metric like energy dissipation.

Declarations
 Funding: The authors did not receive support from any organization for the submitted work.
 Conflicts of interest: The author declares no conflict of interest, financial or otherwise.
 Availability of data and material: Sources of information have been indicated as per their corresponding reference numbers.

Designs
Cell count  Acknowledgements: None. Figure 1 Two possible logic states of a QCA cell Clocking zones in QCA technology NOT gate design in QCA Figure 6