This section aims to review the previous designs in the field of RCA in QCA technology and specify their main features and weaknesses.
The major concepts of QCA and existing logic designs based on QCA technology have been outlined by Chan, et al. . They have studied and implemented the main QCA logic circuits, including five-input majority gate, three-input majority gate, and inverter. To highlight the practical use of utilizing QCA in logic designs, they have proposed a 4-bit ripple adder using a combined concept from the conventional CLA and RCA using 12 inverters, 4 five-input majority gates, and 20 three-input majority gates. The suggested 4-bit ripple adder includes three key blocks, namely, sum block, carry logic block, and propagate and generate (PG) block. They have developed a form of a 4-bit RCA by modifying the carry logic functions combining three-input and five-input majority gates. The offered adder uses 1246 cells with an area of 1.75 µm2 \(\times\)1.43 µm2, and a latency of 5.75 clock cycles.
Also, Chudasama, et al.  have proposed an effective structure of 8×8 Vedic multiplier using Urdhva-Tiryagbhyam sutra, which has been developed using a structure of 4×4 Vedic multiplier as a main block and RCA in QCA. Urdhva-Tiryagbhyam refers to a crosswise and vertical method to find the product of two numbers. The proposed design uses one 8-bit full adder, four 4×4 multipliers, one 3-bit ripple carry adder, and one 8-bit ripple carry adder. The first 8-bit ripple carry adder of multipliers are replaced with an 8-bit full adder to specify the outputs of four 4×4 multipliers. The suggested 8×8 Vedic multiplier requires an area of 18.44 µm2 with 13533 QCA cells and 10.75 clock cycles delay. It requires less cell count and area, but its high complexity remains as a problem.
Safoev and Jeon  have utilized a one-bit full adder to present a 4-bit RCA. It has been designed in a multi-layer manner; the layer of the main cells, in which a majority gate has been placed, and the top layer of the cell, in which an XOR gate has been located. The input and output cells have been placed very smoothly. It means that the proposed design can be simply combined with other circuits. Moreover, the suggested circuit has btter performance in terms of time and area size. The proposed RCA requires 184 QCA cells, 0.1 µm2 area, and 5 clock phases.
Roshany and Rezai  have proposed two novel multilayer QCA architectures, 1-bit full adder, and 4-bit RCA. A new XOR gate architecture has been taken into account to construct the suggested full adder architecture. Moreover, the designed 1-bit full adder has been utilized to design 4-bit QCA RCA. The outcome of the QCADesigner tool confirms that the designed architecture for 4-bit multilayer QCA RCA needs an area of 0.17 µm2, 125 QCA cells, and 5 clock phases. Moreover, the proposed QCA RCA outperforms previous designs, in terms of cost, cell count, and area size.
Aiming to improve the number of cells, the area size, and the amount of delay a novel multi-layer design of QCA-based RCA has been proposed by Seyedi, et al. . The proposed RCA has been designed by cascading several 1-bit full adders, which have been presented in . The utilized full adder contains four main components, two inverter gates, a five-input majority gate, and a three-input majority gate. The proposed 4-bit QCA RCA consists of 112 QCA cells with an area of 0.13 µm2, and a latency of 1 clock cycles.