Since the scaling of transistors is growing rapidly, the need for an efficient alternative for the Complementary Metal-Oxide-Semiconductor (CMOS) technology to obtain further and extra processes in the circuits has known as the main problem. Over the last decade, Quantum-dot Cellular Automata (QCA) technology due to its excellent potential in developing designs with low-power consumption, high-speed, and high-density has been recognized as a suitable replacement to CMOS technology. In this regard, lowering the number of gates, the amount of cell count, and delay has been emphasized in the design of QCA-based circuits. Adders as the main unit in logic circuits and digital arithmetic play an important role in constructing various effective QCA designs. In this regard, Ripple Carry Adder (RCA) is a simple form of adders and due to its remarkable features can be useful to reach circuits with the minimum required area and power consumption. Therefore, in this study, a new design for RCA in QCA technology is recommended to reduce the cell count, amend the complexity, and decrease the latency. To verify the correctness of the suggested circuit, the QCADesigner version 2.0.3 as a well known simulator has been used. The evaluation results confirm that the proposed design has approximately 28.6% improvement in cell count in comparison to the state-of-the-art four-bit coplanar RCA designs in QCA technology. Also, the obtained results designate the effectiveness of the advised plan.
Research Article
A new design for 4-bit RCA using Quantum Cellular Automata Technology
https://doi.org/10.21203/rs.3.rs-569937/v1
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Quantum-dot cellular automata
RCA
Ripple carry adder
QCADesigner
Over the last decades, the Complementary Metal-Oxide-Semiconductor (CMOS) has been considered as a key technology in designing integrated circuits. Since this technology is facing many limitations such as hard lithography, limited power, and short channel effects, researchers have made many efforts to introduce an alternative technology [1]. Recently, Quantum-dot Cellular Automata (QCA) has been known as a promising nanotechnology and become a possible replacement to CMOS technology [2]. Its main aim is to implement rapid processing as well as very low power designs for Nano-sized circuit systems [3]. The designed circuits based on QCA technology have lower power consumption, less occupied area, and lower density [4]. Since the demands for new electronic products with more features are increasing day by day, the importance of density, power consumption, processing power, occupied area, and speed should be considered in the construction and design of this tool [5]. By positioning QCA cells in suitable architectures, which are able to perform computational functions, QCA-based circuits are designed [6, 7].
In order to construct efficient QCA designs, different logical devices such as sequential circuits [8], adders [9], memory [10], counter [11], shifter [12], and ALU [13] have been developed. Adders are the main and integral parts of any digital information processing system, especially logic and arithmetic unit. Generally, a unified hardware with the capable of not only decreasing complexity (cell count) and the area of circuits but also increasing the operation speed is always preferred [14]. Also, Ripple Carry Adder (RCA) as a simple form of adder is pretty flexible and straightforward to any preferred size [15, 16]. Nevertheless, these kinds of adders are relatively slow because carries may propagate across the full adders. Considering its notable features, it can be useful in designing circuits with less required area and power [17, 18]. Since the RCA has gained a remarkable importance in improving QCA designs, current paper aims to introduce a new design of QCA-based RCA. The central contributions of the suggested design are as follows:
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Decreasing the amount of consumed space in RCA designed by QCA technology;
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Reducing the complexity and latency in RCA designed by QCA technology;
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Decreasing the number cells in RCA designed by QCA technology.
The content of the paper is planned in the following way. The previous works are investigated in the next section. In Sect. 3, a new design of RCA is presented. The simulation results are outlined in Sect. 4. Finally, Sect. 5 specifies some hints for upcoming studies and concludes the paper.
This section aims to review the previous designs in the field of RCA in QCA technology and specify their main features and weaknesses.
The major concepts of QCA and existing logic designs based on QCA technology have been outlined by Chan, et al. [19]. They have studied and implemented the main QCA logic circuits, including five-input majority gate, three-input majority gate, and inverter. To highlight the practical use of utilizing QCA in logic designs, they have proposed a 4-bit ripple adder using a combined concept from the conventional CLA and RCA using 12 inverters, 4 five-input majority gates, and 20 three-input majority gates. The suggested 4-bit ripple adder includes three key blocks, namely, sum block, carry logic block, and propagate and generate (PG) block. They have developed a form of a 4-bit RCA by modifying the carry logic functions combining three-input and five-input majority gates. The offered adder uses 1246 cells with an area of 1.75 µm2 \(\times\)1.43 µm2, and a latency of 5.75 clock cycles.
Also, Chudasama, et al. [20] have proposed an effective structure of 8×8 Vedic multiplier using Urdhva-Tiryagbhyam sutra, which has been developed using a structure of 4×4 Vedic multiplier as a main block and RCA in QCA. Urdhva-Tiryagbhyam refers to a crosswise and vertical method to find the product of two numbers. The proposed design uses one 8-bit full adder, four 4×4 multipliers, one 3-bit ripple carry adder, and one 8-bit ripple carry adder. The first 8-bit ripple carry adder of multipliers are replaced with an 8-bit full adder to specify the outputs of four 4×4 multipliers. The suggested 8×8 Vedic multiplier requires an area of 18.44 µm2 with 13533 QCA cells and 10.75 clock cycles delay. It requires less cell count and area, but its high complexity remains as a problem.
Safoev and Jeon [21] have utilized a one-bit full adder to present a 4-bit RCA. It has been designed in a multi-layer manner; the layer of the main cells, in which a majority gate has been placed, and the top layer of the cell, in which an XOR gate has been located. The input and output cells have been placed very smoothly. It means that the proposed design can be simply combined with other circuits. Moreover, the suggested circuit has btter performance in terms of time and area size. The proposed RCA requires 184 QCA cells, 0.1 µm2 area, and 5 clock phases.
Roshany and Rezai [16] have proposed two novel multilayer QCA architectures, 1-bit full adder, and 4-bit RCA. A new XOR gate architecture has been taken into account to construct the suggested full adder architecture. Moreover, the designed 1-bit full adder has been utilized to design 4-bit QCA RCA. The outcome of the QCADesigner tool confirms that the designed architecture for 4-bit multilayer QCA RCA needs an area of 0.17 µm2, 125 QCA cells, and 5 clock phases. Moreover, the proposed QCA RCA outperforms previous designs, in terms of cost, cell count, and area size.
Aiming to improve the number of cells, the area size, and the amount of delay a novel multi-layer design of QCA-based RCA has been proposed by Seyedi, et al. [22]. The proposed RCA has been designed by cascading several 1-bit full adders, which have been presented in [23]. The utilized full adder contains four main components, two inverter gates, a five-input majority gate, and a three-input majority gate. The proposed 4-bit QCA RCA consists of 112 QCA cells with an area of 0.13 µm2, and a latency of 1 clock cycles.
In this section, we use a one-bit full adder as a basic module, which has been proposed by Balali, et al. [24]. The logical diagram of the full adder is shown in Fig. 1. Moreover, the full adder design by QCA technology with a three-input XOR implemented by explicit interactions and half space between QCA-based cells and 3-input majority gates is illustrated in Fig. 2 [24]. The full adder is designed by 29 cells in a coplanar layer and uses 0.5 clock cycles to produce outputs with a 0.04 µm2 area. It uses conventional QCA-based cells and explicit interactions and half space between QCA-based cells in a coplanar layer. A, B, and Cin denote input cells while SUM and CARRY are output cells.
Actually, full adders and RCA circuits are fundamental units in logic circuits and digital arithmetic. RCA's layout is designed and implemented simply, but it is quite slow since each full adder has to wait for the calculated carry bit from the previous one. To overcome this problem, we can reduce the delay in RCAs by decreasing the delay of full adders. The structure of the proposed four-bit RCA architecture is shown in Fig. 3. Also, Fig. 4 indicates the proposed four-bit RCA designed with QCA technology, which has used four full-adders. To design the RCA QCA-based circuit, we use coplanar designed technology and explicit interactions and half space between QCA-based cells. Actually, in this design, the coplanar crossing is allowing for mono-layered circuits. This circuit is designed with a single-layer, and all inputs and outputs are located in one layer. This layer has nine inputs (A0-A3, B0-B3, Cin) and five outputs (S0-S3, Cout). In this scheme, the outputs are not surrounded by other cells, and therefore, they can be accessed easily. In other words, this design does not require a wire to transmit the output signal. Thus, the outputs can be fed to the input of another QCA-based circuit easily.
To verify the effectiveness of the proposed RCA circuit, a comparative study is done in this section. First, the simulation tools and parameters are described, and then the simulation results are investigated.
4.1. Simulation tool
To implement, test, and simulate the proposed four-bit RCA circuit with QCA technology, we used the QCADesigner version 2.0.3. Also, to create test vectors, we used “Coherence Vector” and “Bistable Approximation” engines, which have attained identical outcomes [25].
4.2. Simulation parameters
Simulation parameters are set at their default values in the QCADesigner tool. Table 1 summarizes the QCADesigner parameters required for the simulation of the circuits in QCA technology by “Coherence Vector” and “Bistable Approximation” engines.
Table 1. QCADesigner parameters for “coherence vector” and “bistable approximation”
4.3. Accuracy analysis and comparisons
Figure 6 illustrates the simulation outcomes of the proposed 4-bit RCA circuit in QCA technology by test vectors for A0, A1, A2, A3, B0, B1, B2, B3, and Cin using the values that are shown in Fig. 5. In this test, due to a large number of entries, we tested some samples. The output of SUM0 by applying inputs A0, B0, and Cin (these inputs are applied to the circuit at 0.25 clock cycles) after 0.5 clock cycles is marked with the red rectangle in Fig. 6. Moreover, the Sum1 output based on A1 and B1 inputs (these inputs are applied to the circuit at 1 clock cycles) is produced after 1.25 clock cycles and is indicated with a blue rectangle in Fig. 6. SUM2 output by employing inputs A2 and B2 (these inputs are applied to the circuit at 1.75 clock cycles) is produced after 2 clock cycles and is illustrated by a green rectangle in Fig. 6. Eventually, the outputs of SUM3 and CARRY using inputs A3 and B3 (these inputs are applied to the circuit at 2.5 clock cycles) after 2.75 clock cycles are produced and marked with a black rectangle in Fig. 6. The proposed four-bit RCA in QCA technology has 125 cells with a 0.17 µm2 area and latency of 2.75 clock cycles. The results have confirmed by Fig. 6, where the designed four-bit RCA in QCA technology runs completely and provides suitable proficiency.
Also, the measurement outcomes are described in Table 2. The proposed RCA in QCA technology is better regarding complexity, power consumption, and cell count compared to previous designs. The design owns nearly 28.6% betterment in cell count to the best-presented four-bit coplanar RCA designs in QCA technology.
Over the last decade, to overcome the limitations of CMOS technology, QCA due to its ability in constructing digital circuits with high-speed, high-density, and less energy consumption on the nanoscale has been recognized as a proper replacement. In this regards, full adders are known widely used circuits in QCA-based designs. To obtain circuits with the minimum required area and power consumption, various types of adders such as RCA can be utilized. The current paper proposed a new coplanar design of a four-bit RCA aims to reach a design with less area size, energy consumption, complexity, and QCA cells. To simulate this design, we used both “coherence vector” and “bistable approximation” simulation engines in QCADesigner software version 2.0.3. The simulation outcomes using these simulator engines show that the new four-bit RCA design in QCA technology has approximately 28.6% vantage in cell count compared to previous coplanar designs. The proposed RCA circuit in QCA technology can be employed in the prospect to design n-bit RCA and high-performance QCA technology circuits at the nanoscale. Researchers, engineers, and designers can also use the coplanar crossing, multi-layer crossing, and logical crossing in QCA technology to use the inside cells. Therefore, the proposed scheme can be a fundamental impression of the design of high-speed circuits and other types of adders such as carry save adder and full sub-tractor.
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