DOI: https://doi.org/10.21203/rs.3.rs-580463/v1
In wireless communication networks, the necessity for high-speed data rates has increased in emerging 5G application areas. The existing Power amplifier (PA) topologies reported to date demonstrated their potential in achieving desired Power Added Efficiency (PAE) and linearity with the aid of different efficiency enhancement and linearization techniques. However, these harmonically tuned switching power amplifiers are restricted to narrow bandwidth, which makes them less appealing for broadband applications. Therefore, the challenge of designing a power amplifier with improved efficiency by maintaining linearity for a dynamic range of bandwidth becomes increasingly critical for PA designers. Recently developed class-J PA topology has proven its potential to obtain good efficiency while maintaining the linearity for wide bandwidth applications. This research work presents a methodology to design a 5 GHz Class-J mode PA topology using Silterra 0.13-µm CMOS technology. This research's main objectives are to determine the Ropt of the transistor and design a proper Output Matching Network (OMN) to obtain Class-J PA operation to make it suitable for 5G wireless applications. The simulation results represent that the proposed Class-J PA provides 27 dBm of maximum power output along with a maximum large-signal power gain of 13.8 dB and the small-signal gain of 17dB for a band with more than 500MHz with a 5V power supply into a 50- Ω load.