New Electronically/Resistively Tunable Floating Emulators to Realize Memristor and Inverse Memristor

: This article presents the architectures of two emulator circuits, which realize the behaviour of a floating memristor and inverse memristor respectively. Both the presented emulator circuits are based on modified Voltage Differencing Current Conveyor (MVDCC) and grounded passive elements only. The feature of Electronic/Resistance tunability is found in both the emulator circuits. Furthermore, no employment of any external multiplier circuitry can be viewed as an important advantage of the proposed emulators. Also, the utility of the inverse memristor has also been discussed in theoretical discussions. The simulations have been performed to verify the working of all the presented emulator circuits, under PSPICE environment. Moreover, these MVDCC based emulators are also designed using commercially available ICs, LM13700 and AD844.


Introduction
L. Chua was the first, who laid the theoretical framework of the memristor in his article published in 1971 [1]. After which, various memristor emulators based on different active building blocks (ABBs) have been developed, given in the literature . The detailed comparison of these emulators circuit is presented in Table. 1.

Concept of Memristor and Inverse Memristor
The memductance of an ideal memristor depending upon the flux "ϕ", can be given by Eq. (1) as follows; And v(t) is applied input voltage. For a sinusoidal input, v(τ)=vmsinωt, the current-voltage relationship for memductance GM given in Eq. (1) can be given as; Now, for an ideal memristor, the well-known signature property is the availability of pinched hysteresis loop with cross-over at the origin in transient v-i plot (Plotted in Fig. 1 by using Eq. 3). But, several researchers have also observed and tried to demonstrate a similar type of characteristics in several electrical circuits and components. Due to the absence of other defining properties of ideal memristor, these circuits cannot be considered as ideal memristor and may be termed as non-ideal memristors. The inverse memristor is also a type of non-ideal memristor. The current-voltage relation for an inverse memristor can be defined as, The transient current-voltage characteristics for (Eq. 5), is presented in Fig. 2. It can be observed that the characteristics are found to be exhibiting two lobes in the v-i plane originating from the origin. It can be seen that on raising the value of frequency "ω" gives rise to increase in the area enclosed under the v-i lobes, which is an inverse(contrary)characteristic with respect to an ideal memristor (whose area expands for rising frequencies).
Therefore, due to the fact, inverse memristor does not follow all the signature properties of an ideal memristor, it cannot be used as a worthy element in various memristor related applications. But due to its unique frequency dependence characteristics, it can be used to control and enhance the performance of an ideal memristor as described below. Now, we investigate the effect of connecting inverse memristor in parallel to an ideal memristor (as shown in Fig. 3), considering the case of flux dependent memductance. From Eq. 3 and 5, for the shunt connection of an ideal memristor (M) and inverse memristor (M'), the overall current IParallel flowing through the connection will be the sum of memristive and inverse memristive current as below; From Eq. 3 and 7, the area for ideal memristive case can be given as, And similarly for the shunt connection shown in Fig. 3, it can be found by using Eq. 6 and 7 as; By using Eq. 9, we can plot the area (Amem-inv) versus frequency (ω) response for circuit given in Fig. 3, which is shown in Fig. 4. From this response, it can be observed that controlling the coefficient of inverse memristor, we can alter the frequency dependency of the lobe area. Therefore, we can conclude, connecting inverse memristor in shunt with memristor, we can achieve better controllability over memristor performance in v-i plane.

The idea of MVDCC
The MVDCC (modified VDCC), whose symbol and CMOS implementation have been shown in Fig. 5 and 6 respectively, is a modified version of VDCC. The VDCC, which is an acronym for Voltage Differencing Current Conveyour was first proposed in [35]. It is a popular element and finds its applications in higher order filters, modern oscillators [36][37] and also passive element simulators. It can be found in the articles like [31][32][33][34] that previously some researchers have employed the modified form of VDCC to obtain the Z+ and/or Z-copy current to utilize in their circuit. But it was done without affecting the other port functions of VDCC.
On the other hand, we have taken a Z-copy terminal and equalize the different voltage of Z-and Z+ terminal to the voltage of X port. The resultant modified function can also be understood from the current-voltage relationship of MVDCC shown in Eq. 10.  Where, gm is input stage transconductance. The transconductance of the input stage can be controlled by the biasing voltages VB1 according to the relation given in Eq. 11. )

Proposed MVDCC based floating memristor emulator
The Fig. 7 presents the proposed configuration of the Floating memristor based on MVDCC. It consists of two MVDCCs and three grounded passive elements. The presented circuit does not employ any voltage multiplier circuit/IC, which can be considered as the most attractive feature of this emulator. On applying Eq. 10 and 11, and using circuital analysis for above emulator, the admittance matrix for the given floating circuit architecture is found as; From Eq. 12, it can be easily concluded that this equation is representing an ideal memristor whose memductance GM can be given as, The memductance GM given in Eq. 13 consists of two parts; the first part is representing the time-independent linear part whereas, the second part is non-linear and depends upon the time-varying applied input voltage.
From the designed emulator it can be observed that in MVDCC2 block, the terminals Z-, WP are connected to the ground, which may be considered as a minor wastage of circuit resources. This drawback can be easily overruled by using conventional VDCC in place of MVDCC2.

Frequency-dependent behaviour of proposed memristor
After careful observation, it can be concluded from the memductance of proposed memristor emulator found in Eq. 13, that memductance GM can be viewed as representing a lossy non-linear inductor which is a parallel combination of time-dependent inductor Ltimedependent and an equivalent resistance REq. In the GM expression given in Eq. (13), the time-varying part is corresponding to L time-dependent whose value depends upon the input voltage having a unit of Henry-Volt and Req is represented by the fixed part.
For a sinusoidal input, VmSinωt, the minimum value (at peak input voltage) of the inductance Ltime-dependent (Henry-Volts) can be calculated as, Similarly, the Req can be evaluated as, Now, from Eq. (14) and (15), the time constant of parallel Ltime-dependent-Req of the circuit can be obtained as, From Eq. 14, 15 and 16, τ is obtained as, Time constant "τ" in Eq. 17 can relate to cut-off frequency as follows, Now, "fc" given in Eq. (18) can be used to define the range operating frequency (f) for proposed floating memristor emulator circuit as follows: 1. When f< fc, the hysteresis loop will not be present, due to a large value of timedependent part with respect to the time-independent part. 2. When f=fc, hysteresis loop will be maximum due to equal dominance of both timevarying and constant part. 3. When f>fc, hysteresis will be present in the v-i plane of a memristor

Proposed MVDCC based Floating Inverse Memristor Emulator
The proposed MVDCC based floating emulator structure for an inverse memristor (defined in Eq. (4)), has been shown in Fig. 8.

Figure 8. Proposed Floating inverse memristor emulator based on MVDCC
On applying Kirchoff's circuital laws and using Eq. 10, the admittance matrix of the inverse memristor has been found as; (19) Therefore, using Eq. 19 the inverse memductance for the circuit shown in Fig. 8 can be given as;

Implementation of proposed memristor and inverse memristor emulator using LM13700 and AD844
The section presents the commercial IC-based implementations of memristor and inverse memristor discussed in the previous section. On careful investigation of these circuits it has been found that if we convert these floating circuits into grounded circuits, the commercial IC-based implementation is possible. Therefore, the grounded versions of these emulators have been realized by using ICs LM13700 and AD844S. The IC-based implementation of presented memristor emulator circuit described in Fig. 7 Fig. 8) realized using AD844 and LM13700

Memristor-Capacitor(MC) Low pass filter based on proposed Memristor Emulator
To demonstrate the usability of proposed memristor emulator, a memristor -capacitor (MC) low-pass filter (LPF) has been developed and shown in Fig.11. Figure. 11. MC LPF Filter realized by using MVDCC based memristor emulator (given in Fig. 7) The filter shown in Fig 11 is different from the conventional R-C low pass filter, as in the memristor based filter, the effective resistance offered by memristor depends upon both the input voltage as well as the input frequency.
The expression for cut-off frequency (fc) and gain G (dB) for the filter of Fig. 11 can be evaluated as; 2 2 C G f M C   (21) and Where GM is the memductance of memristor which can be written as; where from Eq. 13, (24) and ) cos( 1 1 2

Simulation Results
For the validation of the reported floating memristor and inverse memristor emulators, PSPICE simulation environment with 0.18um CMOS technology is chosen. The CMOS implemented MVDCC shown in Fig. 6 is used with power supply voltages VDD=±0.9V. And the selected W/L ratio of the employed CMOS transistors in MVDCC implementation is given in Table 2. To verify its behaviour, the simulation has been performed for memristor emulator (shown in Fig. 7) at different values of frequency and obtained results have been depicted in Fig. 12 and 14. The operating values of passive elements have been chosen as; R1=10K, R2=2.5K and C1=0.01nF. The applied sinusoidal voltage has a peak value of Vin=0.1 V. And also, the values of biasing voltages corresponding to MVDCC1 and MVDCC2 have been selected as; VBS1= VBS2=0.2V. Now, it is known that the span of the PHL of an ideal memristor must decrease on increasing the value of applied signal frequency. And the same can be witnessed in the plots presented in Fig. 12 and 13. Now, this contraction of v-i lobes must lead to a shape of a line on the v-i plane passing through the origin, which seems to happen when the frequency is increased further as it is shown in Fig. 13. Now, to investigate the influence of employed passive elements and other quantities such as input voltage and biasing voltage, the excitation signal frequency has been chosen as Fin=100KHz, biasing voltage is kept at VBS1=VBS2=0.4V and peak input value is chosen as Vin=0.1V.
Firstly, the effect of the variation of used grounded resistance R1 has been studied and related simulation results are presented in Fig. 14. It is confirming its resistance tunable nature. On the other hand, when R2 and capacitor C1 were chosen as a variable component, it was observed that variation in the R2 and C1 does not result into significant change in memristor. Therefore, the realized memristor is not tunable through passive elements R2 and C1.
In Fig. 15, the feature of electronic controllability is demonstrated. It can be seen from the figure that variation in biasing voltages VBS2, is producing a significant change in the hysteresis behaviour of proposed floating memristor. Now, the non-volatility property has been checked through simulation. This has been confirmed through subjecting the proposed emulator to a periodic pulse input having on time TON=0.1ns, time-period, Tperiod=0.5ns and the peak value of Von=10mv. The simulations have been performed for both types of connections of memductor namely decremental and incremental type. The corresponding simulations results have been provided in Fig. 16 and 17 respectively, which illustrates the response of memristor current with time. In the plots, the change of memductance is described through the current response, which can be seen as the staircase shape curve plotted over the current pulses. It can be observed from both the plots that for each succeeding applied pulse the height of the generated current pulses found to be decreased and increased(depending upon the case), which follows from the decremental and incremental nature of the employed connection. Next, we have plotted the response of instantaneous memristance over time subjected to sinusoidal excitation. The graph, shown in Fig. 18 has been plotted for Fin=100KHz. During a single period of the input signal, the behaviour of Rin can be observed through the PHL presented in Fig. 12 for 100KHz. The discontinuity at the middle may be because, at this instant the VI contour passes through the origin where the instantaneous resistance cannot be defined. Now, the transient response of voltage and current of memristor have been presented. The current response given in Fig. 20 for the sinusoidal input is presented in Fig. 19. Also, the frequency response plot of the MC low-pass filter based on proposed emulator given in Fig. 11 has been shown in Fig.21 for different values of external capacitance C4. The frequency response has been plotted for the parameter values as; C1=0.01nF, R1=1.5K, R2=1.5K and biasing voltage as VBS1=0.4V, VBS=0.4V.
Furthermore, the transient characteristics of the proposed inverse memristor emulator have also been explored. For the simulation of the inverse memristor emulator presented in Fig.  8, the value of employed passive elements, grounded resistance and capacitance have been taken as R1=1.5K and C1=10nf respectively. The biasing voltage of MVDCC is chosen as VBS2'=0.4V(of second stage) and the peak value of applied input is selected as VP=0.16V. As described in the theory section that area enclosed under the lobes of inverse memristor expands with the increase in operating signal frequency. This frequency dependence can be validated through PHL presented in Fig. 22, 23 and 24. It is verified from the three plots that area enclosed under the lobes increases on raising the operating frequency value. Now, selecting the operating frequency of the proposed inverse memristor emulator as Fin=10KHz and keeping all other parameters constant, the rest of the simulation results are presented. The influence of resistance R3 is studied and derived plots are depicted in Fig. 25. The effect can be clearly observed that the higher value of R3 gives rise to an expansion in the area of PHL. Further, the change in the transient VI characteristics is observed for the variation of biasing voltage VBS2. The corresponding VI curves, shown in Fig. 26, illustrate the effect of biasing voltage on inverse memristor behaviour. Although the effect is not considerable, as second stage of the MVDCC has little effect of applied bias voltage as it is a current conveyor stage.
Furthermore, the working of commercial IC-based implementations of presented emulators given in Fig. 9 and 10 has been validated. Here, we have used the SPICE model of the ICs provided by the Texas-Instruments, which provides the output, in a close match with the physical ICs as per the claim of the manufacturer.
To simulate the memristor emulator based on LM13700 and AD844 given in Fig. 9, the power supply voltage VCC,EE is chosen ±12V and passive elements are taken as; chosen as R1=112K, R2=100K, R3=30K, R4=40K and C1=0.01nF. And also, the maximum value of applied sinusoidal input is chosen as Vm=0.5V. The three plots are given in Fig. 27 illustrate the frequency related characteristics of the PHL of the memristor. As itcan be noticed, that at 25 KHz, the area enclosed by lobe is larger than the area of v-i curve, obtained at 50 KHz. And finally, the size of the lobes become smallest as the frequency is increased up to 75 KHz as shown in Fig. 27. Now, the operation of the inverse memristor emulator given in Fig. 10 can be verified similarly. The circuit is based on LM13700 IC and an AD844 ICs and uses three passive elements. For this simulation purpose of the emulator, the circuit parameters of implemented configuration are taken as; VCC,EE=±12V, R1=112K, R2=100K and C2=1nf. And the pure sinusoidal signal is chosen with a peak value of Vm=0.5V. The transient v-i characteristics of the inverse memristor are plotted in Fig.28, 29 and 30. These three v-i curves are plotted for increasing value of frequency. And it can be witnessed that increasing frequency value giving rise to an increase in the area lobes. It is confirming the described property of an inverse memristor.

Conclusion
The research work was dedicated to the realization of floating emulator configurations of an ideal and a non-ideal memristor based on the MVDCC active element, which is a slightly modified version of popular active element VDCC. The reported floating memeristor emulator consists of two MVDCCs and three grounded passive elements including single capacitance and two resistances. The other presented emulator configuration which realizes a non-ideal memristor is designed using single MVDCC and two grounded passive elements. Both the presented emulator enjoys electronic tunability along with the passive element tunability. The sought after feature of both the reported circuits is no use of any external voltage multiplier circuit/IC which verify the compactness and on-chip realization suitability. This article also describes the utility of inverse memristor for controlling ideal memristive behaviour. For verification of the realized behaviour of proposed emulators, these circuits are simulated using the PSPICE environment using 0.18um technology and all results have been discussed. The given floating memristor and inverse memristor emulators have also been implemented using commercially available ICs; LM13700 and AD844.

Funding Not Applicable 2. Conflicts of Interest
Not Applicable 3. Availability of data and material Data sharing not applicable to this article as no datasets were generated or analysed during the current study.