Study of Analog/Rf and Stability Investigation of Surrounded Gate Junctionless Graded Channel MOSFET(SJLGC MOSFET)

This paper explores the potential advantage of surrounded gate junctionless graded channel (SJLGC) MOSFET in the view of its Analog, RF performances using ATLAS TCAD device simulator. The impact of graded channel in the lateral direction on the potential, electric field, and velocity of carriers, energy band along the channel is investigated systematically. The present work mainly emphasises on the superior performance of SJLGC MOSFET by showing higher drain current (ID), transconductance (gm) ,cut off frequency (fT), maximum frequency of oscillation (fmax), critical frequency (fK) .The drain current is improved by 10.03 % in SJLGC MOSFET due to the impact of grading the channel. There is an improvement in fT, fmax, fK by 45 %, 29 % and 18 % respectively in SJLGC MOSFET showing better RF Performance. The dominance of the SJLGC MOSFET over SJL MOSFET is further elucidated by showing 74 % improvement in intrinsic voltage gain (gm/gds) indicating its better applications in sub threshold region. But the transconductance generation factor of SJLGC MOSFET is less than SJL MOSFET in the subthreshold region. The intrinsic gate delay (ζD) of SJLGC MOSFET is less in comparison to SJL MOSFET due to the impact of lower gate to gate capacitance (CGG) suggesting better digital switching applications. The simulation results reveal that SJLGC MOSFET can be a competitive contender for the coming generation of RF circuits covering a broad range of operating frequencies in RF spectrum.


Introduction
The development of metal oxide semiconductor large scale integration is closely associated with the regular downscaling of its basic element i.e. MOSFET from the starting of 1970 s.
The downsizing of MOSFETs is the ultimate and efficient way to enhance the performance, increase the packaging density, increase the number of functionality in a given chip area, decrease the power consumption if at all the area of the chip is constant [1]. Smaller sized MOSFETs possess electrical characteristics which differ from its bigger size counterpart due to the presence of short channel effects. Hence there is a demand of introducing advanced technologies, novel structures and new materials to fulfil the demand of today's electronic industry and make the MOSFETs suitable for ultra-large-scale integration. Multigate FET (MUGFET) has been proposed in literature where the channel is more electro statically controlled by the gates [2][3][4][5][6]. A junctionless transistor has been proposed in literature as an alternative candidate to overcome the problem associated with thermal budget in the formation of steep S/D junction [7,8]. Mobility degradation in heavily doped channel of JL MOSFET results in lower ON state current and transconductance [9,10]. JL MOSFET relies on bulk conduction and requires gate metal of higher work function to completely deplete the channel during its off state [11].
In the last decades many researchers have put their effort to bring improvement in the Analog/RF performance of conventional MOSFETs using source/drain end engineering [12,13] and gate engineering [14,15] .To mitigate the challenges of SCEs and to achieve high speed performance in wireless RF communications systems, many advanced channel engineered structures have been addressed in literature [12,[16][17][18]. Y.Chen et al. had investigated the Analog / RF performance of graded channel junctionless MOSFET having gate length of 30nm [19]. A. Kranti et al. had put their effort in highlighting the analog performances of SOI DG MOSFET by applying asymmetric channel engineering [20]. The lateral grading of channel shows noticeable enhancement in analog performance of the device due to increase in g m and decrease in drain conductance [21,22].
Many reports are available in literature dealing with the designing problem of RFIC in analysing the high frequency and noise performance [23,24]. All though reports are available in literature showing the analog and RF analysis of different CMOS devices [25][26][27][28][29][30] but a systematic comparison of analog /RF performance analysis in between graded and ungraded channel architecture in surrounded gate junctionless structure is still unexplored.
In this work, we propose Surrounded gate junctionless graded channel (SJLGC) MOSFET as a strong contender for system on chip applications and wireless communication networks. The novelty in present work lies in the architecture of the proposed device as it takes in to account simultaneously the advantages of three architectures such as junctionless architecture (lower thermal budget, easy of fabrication), surrounded gate (channel is more electro statically controlled by the warping of gates and drain current is optimized), graded channel (reduced short channel effect and improved transconductance). Graded channel design in junctionless surrounded gate architecture has not been investigated till now to the best of our knowledge. The fast growing wireless electronic industry need modern technologies in CMOS devices so that these devices can well be applicable for radio frequency/analog/mixed signal applications.
The manuscript is planned as under: introduction related to different reports from literature is presented in section-I. We outline the device description and physical models used during the numerical simulations in section II. In section III, IV we compare the static characteristics, Analog / RF performance of the proposed device with the conventional one. Finally conclusion of this comparison is drawn in the section V.

Device Description and Simulation Model
The 3-D and 2-D cross sectional view of our proposed structure are shown in Fig. 1(a) and (b). The device structural parameters, drain and gate supply sources are chosen as per the guidelines ITRS [31]. The source/drain is heavily doped n type region with doping concentration of 10 19 cm − 3 for both of the devices. This proposed device has a lateral graded doping distribution profile along the channel in the z -direction.
The entire channel length of SJLGC MOSFET is equally divided into two regions where the region towards the source is doped with same doping concentration as the source region (N D =10 19 cm −3 ) and region towards the drain end is heavily doped with a doping concentration(N GC ) of 1.5 × 10 19 cm −3 having length L GC . The length of graded channel region (L GC ) is exactly half of total channel length (L g ) .The SiO 2 is used as the gate oxide material having thickness (t OX ) 1nm. The gate length (L g ) in the cylindrical structure is 30nm. The diameter (2R) of the cylindrical Si body is 10nm which is the width (W si ) of the Si body. The length of source and drain (L S/D ) regions are 20nm.The structural dimension of the conventional SJL MOSFET is exactly same as SJLGC MOSFET except the fact that the source, drain, channel are uniformly doped with n type dopant with a doping concentration of N D = 10 19 cm − 3 .In this work, during our simulation we have chosen the optimized value of the graded channel length i.e. L GC = (L g / 2) [32]. It is the concentration gradient (G = N GC -N D ) at the graded channel region which is responsible for improved performance of SJLGC MOSFET supported by the use of optimized value L GC . But higher concentration gradient leads to reliability issues in fabricating the devices in practical scenario [33]. In the present work the maximum and minimum The structural parameters of the devices are summarized in Table 1. ATLAS TCAD 3-D Device simulator is used for performing simulation in this paper [34]. Carrier transportation mechanism in the silicon body is considered by inculcating drift diffusion model during simulation for channel length L g ≤ 30nm [30,[35][36][37]. The current densities for electron and holes in drift-diffusion model are given by.
Where J P and J n denote current densities for hole and electrons. µ n and µ p are the mobilities of electron and hole. n and p are the electron and hole densities. Fermi statistics constants for electron and holes are denoted by γ n and γ p . The spatial effective masses for electron and hole are m p and m n . The conduction and valence energy bands are denoted by E C and E V . T is the temperature and K is the Boltzmann constants. D n and D p are diffusion constants. The models used during our simulations are specified in Table 2 along with their description.
As the silicon body is heavily doped, a p type polysilicon gate metal having higher work function is used to fully deplete the channel during the off state for both of the device [39]. The threshold voltages of SJLGC MOSFET and SJL MOSFET are at 0.569 and 0.571 V respectively as obtained from the result of simulation where p + polysilicon is used as the gate metal for both of the devices having work function (ɸ m ) 5.0 eV. Hence, we have approximated the threshold voltage of both of the devices at 0.57 V for fair comparison of performances between both of the devices. For regularly down scaled nano MOSFETs with thickness of the channel width (W si ≤ 5nm ), symmetry of the bulk silicon crystal is not preserved. Hence quantization of carriers is required in the channel region due to their confinement in the channel region both in angular and radial direction. As a result quantum mechanical effect is highly necessary [38,[40][41][42][43][44]. But in the present work the thickness of the device is 10nm, hence quantum correction is not required. To solve the set of differential equations and current density equations of charge carriers, Gummel-Newton numerical iteration techniques are used. For result validation, certain parameters of the physical model of our ATLAS TCAD simulator are calibrated with the results obtained from the experiment [45] for n type Si nanowire to obtain the transfer characteristics. To validate our results, we have kept the gate length, oxide thickness, width of the device, doping concentration of S / D /Channel are at 1 μm, 10 nm, 30 nm, 2 × 10 19 cm − 3 respectively as per the experimental data.In the present work, the simulation model is calibrated against the experimental result of Ref. [45] corresponding to V DS =0.05 V for n type Si nanowire where the current is less than 1e-7 A/ µm. A close agreement between simulated results and experimental results are observed in Fig. 2. Once the matching is done, we have used the same model for our present work to analyse the Analog and RF performances.  The enhancement of ON current I D in SJLGC in comparison to SJL as shown in Fig. 3(a) depends on the variation of electron concentration and velocity of electron from source towards drain. Although the diameter of the proposed SJLGC MOSFET is 10nm, still Bohm Quantum potential (BQP) is included in the simulation to take in to account the quantum mechanical effect (QME) [46]. Figure 3(b) shows insignificant quantum mechanical effect on the drain current (I D ) for V DS = 1 V and V DS =0.6 V .Hence in the present work quantum effect is not considered during simulation. Figure 3(c) illustrates the improvement in drain current in SJLGC MOSFET with respect to increased graded channel doping concentration which is due to the increase in the height of concentration gradient but this increased height of gradient imposes burden in fabrication process from reliability point of view [39]. The height of concentration gradient increases when the doping concentration of the graded channel region changes from 1.5 × 10 19 cm − 3 to 5 × 10 19 cm − 3 , resulting in 22.72 % enhancement in drain current as shown in Fig. 3(b).

Static Analysis
To clarify the reason in the increase of I D in SJLGC MOSFET, we have plotted the potential, electric field, velocity of electron, energy band along the channel in Figs. 4, 5, and 6 for both of the devices for their fair comparison. These graphs are plotted by taking cut lines at Wsi / 2.
The centre potential of SJLGC MOSFET increases faster than the SJLMOSFET along the channel from x = 0.020 μm to x = 0.050 μm shown in Fig. 4. This is due to the higher transportation of carriers towards the drain end. There is a small change in potential as shown in Fig. 4 from x = 0.015 μm to x = 0.025 μm. This is due to the absence of     potential towards the source region is the built in potential V bi i,e V bi = (K.T/q)ln(N D / ni ) where ni is the intrinsic carrier concentration in silicon and the potential at the drain region is V bi + V DS [44,47]. The potential at the source region is 0.528 V as depicted in Fig. 4 which is the built-in potential (V bi ). The potential towards the drain region is at 1.028 V as shown in Fig. 4 which is V bi + V DS and V DS is kept at 0.5 V during simulation. A discontinuity in lateral electric field is observed in the channel region creating two different peaks for the proposed device whereas the traditional SJL MOSFET is said to have a single peak of electric field towards drain end as shown in Fig. 5(a). The extra peak of electric field developed in the middle of the channel lowers the impact of electric field created at the drain end for SJLGC MOSFET. Due to lowering of electric field created at the drain, the electrons are strongly pulled from the source towards the channel region in SJLGC MOSFET in comparison to SJL MOSFET. This enhances the transportation efficiency of carrier [48].Improved carrier transportation results in enhancement of drain current (I ds ), transconductance (g m ),cut off frequency (f T ).This extra electric field increases the non-equilibrium transportation capability of carriers in terms of their velocity as shown in Fig. 5(b) near the source end. The magnitude of electric field is the gradient of the potential [49]. In Fig. 5(a), a valley like shape is observed because from x = 0.015 μm to x = 0.025 μm, the change or gradient in potential in Fig. 4 is very less which is clear from the readings of simulation corresponding these particular values of x. Hence, the electric field decreases towards x = 0.025 μm. From x = 0.025 μm to x = 0.030 μm, the change in potential increases in Fig. 4, as a result the electric field increases. The electron velocity is proportionally related to its electric field. Hence electron velocity changes accordingly w.r.t electric field and same valley like shape is observed in Fig. 5(b) at x = 0.025 μm. The energy band diagram of SJLGC MOSFET and SJL MOSFET is shown in Fig. 6. The energy band bends more in SJLGC MOSFET supporting easy flow of carriers from source to drain as the source to channel barrier height decreases [50,51]. This results in increase in drain current.

Analog Performances
Higher value of I D results in higher value of transconductance (g m ) as clear from Fig. 7. The change in drain current is more at V GS =1.1 V as depicted in Fig. 3(a) which illustrates the plot of I D Vs V GS . Hence the transconductance is said to have its highest peak at V GS =1.1 V as evident from Fig. 7. SJLGC MOSFET exhibits lower drain to source conductance (g ds ) as compared to SJL MOSFET as shown in Fig. 8. The cause behind this is the discontinuity in electric field at the position along the channel where the channel is graded with higher doping concentration which redistributes the electric field mainly towards the drain end .When V DS increases in the region of saturation, the highly doped region of channel absorbs the extra drain voltage beyond saturation and restricts the further punch through of electric field into the source end. This physical phenomenon is called screening effect which is the main cause of lowering the g ds [52].
Transconductance generation factor (TGF) is the ratio of transconductance (g m ) to the drain current (I D ). It is one of the key performance parameters considered in the design of subthreshold low power applications. The traditional SJL MOSFET possesses a slightly higher value of TGF in comparison to our proposed device as depicted in Fig. 9. This lower value of TGF for SJLGC MOSFET will not be regarded as its demerit as a very less power is consumed in the sub threshold region.
Intrinsic gain is referred as the ratio of transconductance to drain conductance (g m / g ds ). SJLGC MOSFET outperforms the conventional SJL MOSFET device in terms of intrinsic   Fig. 10. This result is due to lower value of g ds possessed by our proposed device. SJLGC MOSFET posses higher value of intrinsic gain in the subthreshold region, although both of them are having same intrinsic gain for higher value of V GS .This enhances the analog performance of the proposed device as analog circuits, designed for ultra low power applications, are operated in the subthreshold region [53] .

RF Analysis
In Figs. 11, 12, and 13, we have compared the inter electrode capacitances of the proposed device with the traditional one such as gate to drain capacitance (C GD ), gate to source capacitance (C GS ), gate to gate capacitance (C GG = C GS + C GD ). For RF analysis of the devices, we have chosen the frequency of the test voltage at 1 × 10 12 Hz .
The use of higher doping concentration at the middle of the channel results in lower value of C GS and higher value of C GD in SJLGC MOSFET in comparison to SJL MOSFET as shown in Figs. 11 and 12. C GD of SJLGC MOSFET in the present work is higher than that of SJL MOSFET because the graded channel portion towards the drain end is doped with higher concentration (1.5 × 10 19 cm −3 ) which results in creating different sheet charge densities along the direction of transportation [19].
The discontinuity in electric field profile in SJLGC MOSFET along the channel reduces the inversion charges towards the source end of the channel, thereby making the V GS less effective for the inversion of channel near the source region. Due to this reason the value C GG decreases in SJLGC MOSFET in comparison to SJL MOSFET as indicated in Fig. 13(a). The variations in all the inter electrode capacitances with respect to multiple frequencies are shown in Fig. 13(b). The inter electrode capacitances are almost constant with a  negligible variation with respect to frequency, representing themselves to be frequency independent terms [54,55].
In this section RF performance of the proposed device is compared with the conventional one with respect to different FOMs such as cut off frequency (f t ), maximum frequency of oscillations (f max ), intrinsic time delay, critical frequency (f k ).
The minimum frequency at which the current gain attains a value of unity is regarded as the cut off frequency (f T ). f T is the key performance parameter for comparing the devices used in high speed digital switching operation. The frequency at which the maximum unilateral power gain falls to 0 dB (unity) is considered as the maximum frequency of oscillation (f max ). f max is important for comparing the devices used in tuned radio frequency amplifiers. Intrinsic delay (ζ D ) is another performance metric for analyzing the devices applied in digital high speed applications. The evaluation of f T , f max, ζ D are done using the following analytical expressions [56][57][58][59][60][61].
The incorporation of graded channel in the proposed device increases the electrons mobility by weakening the electric field in the drain end. This results in improvement of cut off frequency of the proposed device as depicted in Fig. 14. SJLGC MOSFET exhibits improvement in f max as shown in Fig. 15. More number of free charge carriers are accumulated in the channel region with the increase in V GS , as a result drain current (I D ) and transconductance (g m ) increases. At higher value of V GS , the electric field is maximized and the electron velocity is saturated resulting in decrease in g m [62]. Both cut-off frequency (f T ) and maximum frequency of oscillation (f max ) are proportional to transconductance (g m ) as evident from Eqs. (3) and (4). When V GS increases from sub threshold regime, f T rises due to higher g m and lower gate to gate capacitance (C GG ). The fall in f T at higher value of V GS is due to the simultaneous impact of increasing C GG and limiting transconductance (g m ) [63].The peak values of f T for SJL and SJLGC MOSFETs are at 370 GHz and 536 GHz, resulting in a improvement in 45 %. f max shows the same behaviour as f T with respect to V GS . This is due to the compensation of increase in parasitic drain to source capacitance with decrease in g ds . f max is having its peak value at 1705 GHz and 2185 GHz for SJL MOSFET and SJLGC MOSFET respectively showing an improvement of 29 %.Intrinsic gate delay is one of the important parameters as it limits the operating frequency of MOSFET [64]. The reduction in intrinsic delay of SJLGC MOSFET is shown in Fig. 16. The decrease in C GG and increase in I on of SJLGC MOSFET lead to the reduction of intrinsic delay as compared to the conventional SJL MOSFET. Lower value of intrinsic delay of SJLGC MOSFET enables itself to operate at higher frequency which is needed for RF applications [65].
Stability of LNA should be investigated for the designing of RF and microwave amplifiers. The best possible way to inquiry the stability is to evaluate the stern's stability factor (K).The value of Stern's stability factor( K) indicates how far the system is stable in terms of its resistivity to oscillation. The frequency at which K is exactly equal to 1 is the critical frequency (f k ) [66,67]. The expression for K is given by Where S 11 , S 22 are reflection coefficients and S 12 , S 21 are transmission coefficients. Δ is the S matrix which is defined as: Δ ¼ e S 11 Â S 22 ð ÞÀ S 12 Â S 21 ð Þ . (K > 1 ) and ( Δ ˂ 1 ) are the prerequisite criterion for the concerned device to be stable [68] .The more the value of K, the more stable will be the system [69].The value of K is more for SJLGC MOSFET than for SJL MOSFET at higher frequencies as indicated in Fig. 17. The critical frequency f K for SJLGC and SJL MOSFETs are 1500 GHz and 1800 GHz respectively as evident from Fig. 17 and shows an improvement of 18 %. This result suggests that SJLGC MOSFET attains stability from 1500GHz without the need of any complex hardware circuitry for stabilization. The comparison of all the FOMs in between the two devices that we have discussed so far are summarized in Table 3 given below:

Conclusions
This paper mainly focuses on the impact of graded channel in the surrounded gate junctionless architecture on the Analog and RF performances with respect to the key performance parameters such as TGF, intrinsic gain, cut-off frequency (f T ), maximum frequency of oscillation (f max ), stern's stability factor (K), Critical frequency (f K ). The result of performance comparison between SJLGC MOSFET and SJL MOSFET shows an enhancement in Analog and RF performances for the proposed device. The cause for this improvement is the existence of additional electric field peak at the position along the channel where the channel is graded. This additional peak speeds up the transportation capability of the charge carriers and the energy band bending is more resulting in higher drain current in SJLGC MOSFET. There is an improvement in drain current(I D ), f T, f max , and f K by 10.03 %, 45 %, 29 % and 18 % respectively in SJLGC MOSFET showing better RF Performance. SJLGC MOSFET shows 74 % improvement in intrinsic voltage gain (g m /g ds ) than SJL MOSFET indicating its better applications in sub threshold region. Hence, in this paper, we conclude that SJLGC MOSFET is an attractive and competitive contender of the advanced structure MOSFETs for high speed RF applications with improved stability. SJLGC MOSFET is also a promising candidate for designing a stable LNA used in ultra-wide band RF amplifiers.