A Novel Method of Designing an all Optical 3-Bit Asynchronous Counter

: In digital signal processing and data communication system in optical domain it is paramount important to count the pulse number of any device or processor and hence optical counter for fast counting. In this letter the authors propose a new method to implement an all-optical 3- bit asynchronous binary counter comprising all-optical T flip flops which works based on the polarization switching characteristics of SOA, and frequency encoded data have been used for communication purpose. Use of Frequency encoding technique in the proposed scheme makes it attractive and effective one in various aspects in wave division multiplexing based communication network. Simulation aided results support the practicability of the proposed scheme.


Introduction:
Present day's communication demand fast and secure data processing. So, one of the important way-outs is to switch over our interest from electronic to optical communication. To implement our desired all optical communication we need optical logic gates, processors, memory unit, etc. Counter is such an important processer which is used to count number of pulses in case of data transmission. Counter is a one kind of registers which can go through a certain determined sequence of states. A Clock pulse, pulses originated from outside source maintaining a specific time interval or some random pulses can be used as input pulse. The sequencing of the state follows binary pattern or any other kinds of sequence. Optical counter is considered as a key element because in optical packet switching it could be used as packet buffers, as frequency converter, and also finds potential applications in many more optical high speed data transfer networks.
All optical synchronous counter has been demonstrated by Tamer [9 ] based on two coupled polarisation switches(PSWs)flip flops; Asynchronous counter based on JK flip-flop memory has been described by T.A .Moniam [10]; Synchronous counter by exploiting Kerr nonlinearity has been reported also by Mitra et al. [11 ]. In this letter the authors proposed an all optical 3bit asynchronous counter using T flip flop which works on the basis of frequency conversion and polarisation switching action( PSW)of semiconductor optical amplifier(SOA)with the help of frequency encoding technique. Several types of technique for encoding/decoding of optical data for example spatial encoding [12] , intensity encoding [13,14], polarization encoding [15], phase encoding [16 ] , etc. has been reported till date. But all these mentioned techniques have some own limitations. The frequency encoded data have been utilised hare because of it's unique nature of constancy in case of absorption, refraction, reflection, etc, throughout the entire communication. Here binary '0' state has been encoded by the optical signal of 'ν0 ' frequency and binary '1' state is encoded with the help of optical signal of 'ν1 ' frequency. The article is organised as follows: Section-1 is the introduction of the proposed scheme. In section-2 switching and frequency conversion action of the SOA has been explained. Section-3 and Section-4 covers the design of the two input NOR gate and three input AND gate circuit and explains their operation of it supported by the simulation results.Section-5 deals with the circuit design, its operation followed by the simulation results of the JK flip flop. In Section-6 the design and operation of the proposed asynchronous counter is explained, and lastly Section-7 contains discussion of the proposed scheme.

Working principle of polarisation switch :
The proposed optical circuit works on the principle of polarization switching action of SOA [17,[20][21]. A high intensity optical beam is injected to the SOA as the pump beam. Another beam of comparatively low intensity is used as the probe beam of SOA via an attenuator as shown in Fig-1. The function of polarization controller (PC) is to maintain the polarization state of the probe beam. The polarization beam splitter (PBS) splits the amplified probe beam into two components. When the pump beam is absent, the amplified power of the probe beam will appear at the output port-2, but in the presence of pump beam of sufficient intensity almost all the power will appear at output port-1. The mechanism of the nonlinear polarisation rotation of the probe beam in SOA is based on the works of Dorren, et al. [17] The difference in phase between the TE and TM mode is given by equation   difference is  = 180 0 between two modes [18] The power variation at port-1 and port-2 with the input pump power are shown in Fig.3.and Fig.4, respectively. The values of some useful parameters used for SOA simulation are: Γ TE = 0.2 , Γ TM = 0.14, α TE = α TM = 5, ξ TE = 7.0x10 -9 ps -1 , ξ TM = 6.5x10 -9 ps -1 , vg TE =vg TM = 100 μm /ps ,F=0.5,N0 = 10 8 , L = 800 μm, T1 =500 ps, αint TE/TM = 0.27 ps -1 , e = 1.6 x 10 -19 C .The optical power of the probe beam used here is 0.03 mW [19].

Scheme of two-input NOR gate:
The proposed optical two-input NOR gate is designed with three polarisation switches (PSW) P1, P2 and P3, two DMUXs (D1 and D2), and two MUXs (M1 and M2), as shown in Fig.5. Input beam 'A' is directly applied to D1 whereas the input beam 'B' is applied to P1 via attenuator. D1 routes the input beam 'A' in accordance to the frequency. Its channel -1 passes the frequency ν0, whereas channel-2 passes ν1 frequency. Output port-1 of P1 is connected to the input of D2.Channel-1 and Channel-2 of D2 also carries the beam of frequency ν0 and ν1, respectively. Channel-1 of D2 is connected to P2 and it serves as pump beam of P2. Channel-2 of both the DMUXs are connected by MUX (M1), and the output of M1 is injected as the pump   Table 1.

Case-1: A= B=ν0
Here input A (ν0) transmits through the channel-1 of D1 and works as the pump beam for P1. On the other hand input B (ν0) acts as the probe beam of P1. As pump beam is available for P1, it switches the applied probe beam to it's port-1 which is then reaches to P2 via channel-1 of D2. This beam works as the pump beam for P2 and it switches the probe beam (ν1) at the port -1 of P2. Finally this ν1 frequency beam passes through M2 and appears as the final output. Here P3 not getting any pump does not contribute to the final output.  beam, probe beam appears at port-1 of P1,and after being channelized through channel-2 of D2 and through M1 is injected as pump beam for P3. As P3 gets the pump beam, it switches it's probe beam (ν0) to port-1, which gives the final output via M2.

Case -3: A = ν1 , B = ν0
Here input beam A(ν1) works as the pump beam for P3 after passing through channel-2 of D1 and M1 respectively. Input beam B (ν0 ) is applied as the probe beam to P1,but not receiving any pump beam its port-1 remains off. Consequently P2 also remains off. In this case P3 receives pump beam, so it switches the probe beam (ν0) to its port-1,which gives the final output after passing through M2.

Case -4: A= B= ν1
Here function of both input beams is same as mentioned in the previous case. Input beam A and B works as the pump and probe beam of P3 and P1 respectively . But as P1 does not receive any pump beam , it's port-1 remains off. P2 also remains off as it does not receive any pump beam from D2. On the other hand P3 receiving the pump beam, switches the probe beam (ν0) to its output port-1 ,which gives the final output via M2.
In Fig. 6   Now working of the proposed scheme of the AND logic gate is explained as below: Input beam A being of frequency ν0 ,it passes through channel-1 of D1 and acts as the pump beam of P4 via M1. Input beam B (ν0) and C (ν0 or ν1 ) are applied as the probe beams to P1 and P2, respectively. As both the PSW (P1 and P2) does not receive any pump beam ,so they remains inactive. So P3 also remains inactive .While on getting the pump beam P4 switches the applied probe beam of frequency ν0 to its output port-1 which finally gives the output through M2. Therefore, whatever be the frequency of the input C, the output gives the beam of frequency ν0 for this case. transfer the probe beam to it's port-1. As a result ν0 frequency arises at the port-1 of P1 which subsequently serves as pump beam for P4 via channel-1 of D2 and after that through M1. Input beam C ( ν0 or ν1) is used as probe beam to P2. But P2 not getting any pump beam remains off. Consequently P3 also remains off. Now as P4 receives the pump beam, it switch the probe beam of frequency ν0 to its port-1 and that gives the final output through M2. Here also same situation happens in terms of the output beam frequency as the earlier two cases.

Case-4: A = B = ν1, C = ν0
Now input signal A(ν1) is utilized as pump beam for P1 after it passes through the channel-2 of D1. Input beam B (ν1) serves as the probe beam for P1 and in the presence of pump signal it appears at port-1 of P1. It is then acts as pump beam for P2 via channel-2 of D2. Input beam C (ν0) serves as the probe beam for P2. As P2 gets the pump beam, it transfers the probe beam to its port-1. Thus at port-1 of P2, ν0 frequency appears which is then used as pump beam for P3 through D3. P3 switches the applied probe beam of frequency ν1 to it's output port-1 .Thus ν1 frequency is obtained as the final output through M2. Here P4 does not get any pump beam ,so it remains off.

Case -5 : A=B = C = ν1
Now via channel-2 of D3. As a result P3 switches the probe beam (v1 ) to it's port-1 .Thus v1 frequency appears as the final output. In this case ,not getting any pump beam P4 contributes nothing towards the final output.
In Fig 8 .the power spectrum of the simulated input and output signals are shown for the proposed AND gate.

Scheme of All optical clocked JK flip flop:
The proposed JK flip flop circuit comprises two 3-input all optical AND gates, two 2-input all optical NOR gates, two input named as 'J' and 'K' and a clocked pulse which is also given as the input to the both AND gates. We will discuss the whole The frequency encoded input-output form of JK flip flop is shown in Table 3. In this case both the AND1, AND2 gives the beam of frequency ν0 at their respective outputs. Now as is of frequency ν0 and it is fed to NOR2, so it get both the inputs as the beam of frequency ν0 resulting 'ν1' frequency as output. Likewise n ̅̅̅̅ is of frequency ν1 which is fed to NOR1. So on getting two different frequency signals as inputs, it gives the frequency 'ν0' as output. Finally we get +1 as ν0 and + 1 ̅̅̅̅̅̅̅̅̅̅ as ν1, which is same as the previous state outputs.  In this case AND1 gives ν0 frequency at the output but AND2, getting one of the inputs as ν0 frequency, gives ν0 frequency as its output. Now as is of frequency ν1 and it is fed to NOR2 resulting a frequency 'ν0' as output. Similarly NOR1 getting both the inputs as ν0 gives 'ν1' output. As a result we gets +1 = ν1, + 1 ̅̅̅̅̅̅̅̅̅ = ν0, which is also same to its previous state. Here as AND2 gets all its input beams of ν1 frequency, it gives output ν1, but AND1 gives the frequency ν0 as outputs.
which is the previous state output is of frequency ν0 and it is fed to NOR2 resulting a frequency 'ν0' as it output. Now this output is fed to NOR1 and it gives 'ν1' at the output. Finally we get +1 as ν1 and + 1 ̅̅̅̅̅̅̅̅̅̅̅ as ν0,i.e. output of the present state +1 toggles to ν1 from ν0, which" SET" the flip-flop. In this case AND2 gives ν0 output but AND1, getting one of the inputs as frequency ν0 gives the ν0 as its output. Now, as 'Qn ' is of frequency ν1 and it is fed to NOR2, it gives frequency' ν0' as output. Similarly NOR1 getting both the inputs as ν0 gives 'ν1' output. As a result we gets +1 = ν1 , + 1 ̅̅̅̅̅̅̅̅̅ = ν0 which is also same to its previous state. Here as AND1 gets one of its input of ν0 frequency, it gives output ν0. Similarly AND2 gives the frequency ν0 as outputs.
which is the previous state output is of frequency ν0 and it is fed to NOR2, which getting both the inputs as ν0 frequency gives 'ν1' as it output. When this ν1 frequency is fed to NOR1 which is getting the inputs of ν0 frequency gives 'ν0' frequency as output. Finally we get +1 as ν0 and + 1 ̅̅̅̅̅̅̅̅̅ as ν1 , which are the previous state outputs.
Case 6 : J = ν0 , K= ν1 (considering at this instant the previous output sate = ν1 , In this case AND1 receives all of its input as ν1 frequency gives ν1 output but AND2 gives the ν0 as its output. Now as n ̅̅̅̅ is of frequency ν0 and it is fed to NOR1 gives frequency ' ν0' as output. This ν0 frequency along with the output of AND2 gives the NOR2 output ' ν1'. As a result we gets +1 = ν0, + 1 ̅̅̅̅̅̅̅̅̅ = ν1, Thus the output of the present state +1 toggles to ν0 from ν1, which "RESET" the flip flop. In this situation AND2 gets all of its inputs of frequency ν1 gives output ν1, whereas AND1 gives output of frequency ν0. which in this case is taken as ν0 and fed to NOR2 gives frequency ν0 as its output.NOR1 is fed by + 1 ̅̅̅̅̅̅̅̅̅ and AND1(frequency ν0) also gives ν1 as output.so we get +1 = ν1, + 1 ̅̅̅̅̅̅̅̅̅ = ν0. after getting all its input of frequency ν1 also gives output of ν1 frequency, on other side AND2 gives ν0 as its output. Output of AND1 and n ̅̅̅̅ are fed to NOR1 gates and it results a frequency ν0 as its output. Whereas NOR2 being fed by AND2 and Qn+1 gives ν1 output .As a result we get +1 = ν0, + 1 ̅̅̅̅̅̅̅̅̅ = ν1 .

Design of the all optical 3-bit asynchronous Counter :
In a counter circuit on application of number of input pulses a set of unique combinations of output is produced and that number of unique outputs is called the mod number or modulus of the said counter. An n-bit binary counter comprising n number of flip-flops is able to count in binary from 0 to 2 n -1 number of pulses. Here    Here all the T inputs are connected together and given a High input (Beam of frequency ν1). The counting sequence of 3-bit asynchronous counter is given in the Table.5. The output waveform of the proposed counter is shown in Fig.13. Table 5. Counting sequence of a 3-bit counter operation starts working only when CLK pulse is present. The counter is first resets by making the outputs Q2Q1Q0 at ν0 state .Now when first pulse is introduced LSB Q0 becomes ν1, Q1 is in a condition to toggle if the next clock pulse has arrived. When the next pulse comes Q1 and Q0 simultaneously toggle. The final output taken from the consecutive Q2Q1Q0 will be ν0 ν0 ν1 after the first pulse, ν0 ν1 ν0 after the second pulse, and after passing of the seventh pulse the counter will count ν1 ν1 ν1 as the final output.

Discussions:
In this paper authors have exploited the nonlinear rotation of the state of polarization(SOP) of the probe beam in semiconductor optical amplifier(SOA).
Commercially available bulk JDS-uniphase SOA is used here to design the proposed circuits. [22][23]. In this SOA ,the required power of the pump beam is about 0.5 mW to the switch the probe beam from one port to another [24] . When pump beam is not present ,the SOA does not show any kind of nonlinearity. In this case the required probe beam power is restricted to 0.03 mW to have a faithful operation. To design 2-input NOR gate and 3-input AND gate at a time atleast two probe beam source is required. There are two AND gates, two NOR gates, in total four such gate is present in the proposed circuit of JK flipflop. So 2 x 0.03 x4 mW=0.24 mW optical power is required for the probe beams. Now in the circuit both the outputs Qn and n ̅̅̅̅ are feedback to the inputs. power of the both input is 0.5 mW each. So the power of the inputs J and K should not be greater than 0.03 mW.
There is a clock inputs also. So power of the inputs = 0.03 x 3 =0.09 mW. Therefore the total optical power requied to operate a JK flip is = 0.24 + 0.09 = 0.33 mW. Thus the requirement of power to operate 3-bit asynchronous counter is 3 x 0.33=0.99mW, i.e., almost 1mW. For proper biasing of the PSW, 160mA current is required. So according to our proposed circuit total 3 x 14 x 160 = 6.72 A current is required.
There must be some delay in any circuit. The delay due to feedback loop, and the duration of a clock pulse should be greater than the gain recovery time of SOA. The gain of the SOA remains constant in the C band. Thus it is best to select the frequencies for encoding data from this regime. We have chosen the frequency for encoding the data as 1.9317 x 10^14 Hz (wave length 1552 nm.)for ν0 and 1.9255 x 10^14 Hz (wavelength 1557nm.) for ν1, respectively. The authors have considered a frequency encoded clock, which supplies optical beam of frequency1.9255 x 10^14 Hz (wavelength 1557nm.) and 1.9317 x 10^14 Hz(wave length 1552 nm.)

Conclusion:
Our