Software Design of VerilogHDL Code Generation for Ladder Diagram and Data Acquisition Using LABVIEW

Powerful advantages of programmable logic controller (PLC) dominate process industries. Scan time of PLC increases with the number of inputs, rungs added in ladder diagram (LD). Researchers have identified and proved that field programmable gate array (FPGA) is more suitable than PLC for high speed applications. PLC executes the instructions represented through LD. PLC programmers are not familiar with FPGA programming. But, FPGA does not support LD based programming. This work has developed application software to generate equivalent VerilogHDL code for LD using LabVIEW. Novelty in this work is that each rung is defined using an "assign" statement which helps simultaneous execution of all the rungs. A data acquisition system was created to monitor the digital signals handled by the FPGA. The software was verified with a case study of substances mixing and traffic light control system.


Introduction
Programmable logic controller (PLC) is best utilized for industrial automation by many process industries [1,2]. Industrial automation views the process industry in terms of number of analog and digital signals to be processed. Figure 1 shows the establishment of digital input module (DIM) and digital output module (DOM) with PLC. Digital input module uses multiplexing technique to receive digital inputs from the plant and store them in memory. A suitable data transfer technique transfers these digital data to PLC. Expansion connector connects more number of DIMs to PLC [3,4]. In one way, this option shows the capability of PLC in processing higher number of digital signals.
But, it actually increases scan time which indirectly impacts the process condition [5]. PLC uses these data whenever it executes ladder diagram (LD). The time required for this entire process is not convincing for high speed applications since the program executed by PLC is sequential [6,7]. The LD faces problems like data dependency [8], output dependency, missing of input signals and increase in logic scan time along with the increase in the number of rungs. LD in Fig. 2a is an example for data dependency problem. Output2 depends on the current value of Output1 which will be available only after the execution of first rung. Assume that the PLC generates Output1 and Output2 at every 25th and 30th milliseconds respectively. Result of Output2 will be wrong if the Input1 changes between 25 and 30th milliseconds.
In case of output dependency, there could be a situation in which an output depends on the activation of any one of the input as shown in Fig. 2b. When the Input1 is at high state, the Output1 is also in high state. However, the status of Output1 is based on the condition of Input2 also. In fact, it is the programmer's mistake wherein both Input1 and Input2 shall be connected in parallel and the output to Output1. Still, output dependency problem occurs. All such problems lead to poor processing condition.
The problems of data dependency, output dependency can be eliminated by using field programmable gate array (FPGA) to execute LD in terms of Hardware description Language (HDL) code as the execution is parallel and hardware based [9]. The effect of  Table 1 compares the advantages of using FPGA with processor in a process.
Even though FPGA is a better alternative for PLC, industrialists waver to replace it with latest technology [12,13]. PLC programmers are familiar with ladder logic program only. FPGA cannot process LD.
Researchers have already focused this problem and developed embedded system based solutions [14]. It is also attempted to develop PLC which can be realized into an FPGA chip [15,16]. Since FPGA overcomes the problem of sequential execution incurred by a processor [17], the proposed design used a direct approach to convert LD into Verilog code.

Ladder Diagram to HDL Code-A Direct Mapping
PLC manufacturers define their own conventions for the elements to be represented in LD [18]. Therefore, representation of inputs, outputs, addresses and other functional blocks differs with respect to the manufacturers [19]. This requires the programmers to pay attention to the naming followed for a particular PLC irrespective of their programming skill. LD has many function blocks and the basic elements called Normally Opened (NO), Normally Closed (NC), output and timer coils. The logic of entire LD is mainly decided based on the connections established by the basic elements. Hence this work has focused on the basic elements. Solution for the conversion of LD into HDL code has been developed using data flow graph [20], state chart [21,22]. This work has concentrated on how to directly generate HDL code from the LD for each rung.
The process of LD development to FPGA implementation is done in two stages. In the first stage, Laboratory Virtual Instruments for Engineering Workbench (LabVIEW) application software generates an equivalent VerilogHDL code for the LD developed in LabVIEW. Thus generated code can be implemented into an FPGA. Suitable synthesis software is used in the second stage to convert VerilogHDL code into a bit file. Synthesis Time required to execute a rung is the time required to store data in memory from fields, fetch all the necessary data from memory, execute the logic and store the output data in memory [10] Delay time of the logic is the time required to execute a rung It executes rungs in sequential manner [11] It converts all the rungs into digital logic and hence establishes simultaneous execution It stores ladder logic execution output(s) in memory one by one software is normally provided by FPGA vendor. Therefore, this work has focused its attention on the synthesis process of LD to VerilogHDL code. Figure 3 depicts the proposed novel idea of converting LD into VerilogHDL code. Each rung in an LD is represented using 'assign' statement. The nature of 'assign' statement in VerilogHDL language is its concurrent execution. Therefore, this method overcomes the problem of sequential execution of LD in a rung by rung basis by a processor. Again, elements mentioned in a rung are also executed sequentially. However, if any one of the variable in an 'assign' statement depends on the output of another 'assign' statement then the concept of concurrent execution would become invalid.
Synthesis of 'assign' statement results into combinational circuits. Use of timer element in the LD demands clock signals and this creates sequential circuits. LD elements considered in the synthesis process are NO coil, NC coil and timer [23]. Three timers considered for the purpose of synthesis in this work are pulse timer, on delay timer and off delay timer. LabVIEW invokes the pre-written VerilogHDL code whenever a particular type of timer is included in the LD. A complete VerilogHDL code for the entire LD will be generated when the "generate code" option in the application software is chosen. Figure 4 shows the VerilogHDL code of the logic gates equivalent to the LD representation that has used "assign" statement. This has been the basic synthesis model of LD to VerilogHDL code conversion of this work.
'AND' logic gate is realized when two 'NO' coils are connected in series. It becomes a logical 'OR' gate when these two coils are connected in parallel. Similarly, 'NOR' and 'NAND' gates are realized by connecting 'NC' coils in series and parallel respectively. VerilogHDL code shown in Fig. 4 will be packed into a module when all these rungs are programmed into an LD to ensure concurrent execution. The normal way to execute O1 is to store O0 in a memory element and use this data whenever the second rung is under execution. Memory element requires a clock pulse and also creates delay. On the other way, the equivalent VerilogHDL code for this LD is generated and synthesized to generated RTL circuit as in Fig. 5.
The Boolean expression for the LD can be derived as below. Equation (3) avoids the usage of memory element as O0 is directly connected to the second rung. This facilitates merging of two rungs into a single. Therefore, the synthesis software is intelligent enough to generate an optimized Register Transfer Logic (RTL) circuit, utilize the FPGA resources in an efficient way. Hence, it is enough to generate the equivalent HDL code for the given LD. In LDs, outputs are sometimes used as inputs. Therefore, declaring the output as bi-directional in VerilogHDL code, it can be connected as an input to another logic gate. This work has followed three steps to generate VerilogHDL code from the LD.
• Develop LD in the front panel of LabVIEW.
• Generate Verilog code for the present rung.
• Generate Verilog code for all the rungs.

LD elements description in LabVIEW
Basically, LabVIEW software was developed for virtual instrumentation. Apart from instrumentation, it can be used in many broader areas like signal processing, communication, image processing, control design, simulation, data analysis etc., It offers a graphical programming environment. Programming can be done either at low level or functional level. This work has used LabVIEW to develop LD in its front panel and generate equivalent VerilogHDL code from it. This work has mainly used the functions of Event and Case structure. Rungs in an LD are executed in a series manner. Efficiency of execution can be improved by rearranging them without disturbing the logic involved in it. Representation of LD using enhanced data flow graph (EDFG) has been discussed in [23]. This work has involved EDFG to represent LD elements as and when it is required.

NO/NC -Series
Output of an NO coil follows its input. In case of NC coil, the output is the inverse of its input. It is possible that a rung can have more than one NO coils connected in series or NC coils connected in series or the combination of both NO and NC coils connected in series. Table 2 indicates the representation of NO and NC coils and the possibilities by which these two can be connected in series using EDFG. Variable names assigned for the inputs and outputs and the functions of the LD elements discussed in this work are based on the specifications mentioned by the IEC6113-3 standard [24].
Respective equivalent VerilogHDL codes for the Sl.No 3, 4, and 5 are listed below.
(1) In LabVIEW, Series event structure is invoked when the user clicks on the "SERIES" control button. This structure is used to draw the symbol of NO/NC coil. Figure 6 shows the block diagram (coding part) for series or parallel connection of elements in LD. Case structure inside this event structure will check for the coil type (NO/NC). After choosing the coil, this particular coil will be included in LD; name assigned for this will be stored in memory. This event structure can be called 'n' number of times to connect 'n' elements in series. However, this is to be limited in the practical scenario.

NO/NC -Parallel
It is possible that NO and NC coil can be connected in parallel. Table 3 explains how these connections can be represented using EDFG. It shall be noted that the representation has been explained for only one NO and NC coil. However, in practice, more number of NO / NC coils are used in the LD.
Respective equivalent VerilogHDL code for the Sl.No 1, 2, and 3 are listed below.
• assign out = in1 | in2; Figure 7 shows a rung in which an NC coil (In4) is connected in parallel with the three NO coils (In1, In2, In3) that are connected in series. It also indicates how this rung is denoted using EDFG. Since the NO coils are logically ANDed with each other, the EDFG can be simplified as shown in the Fig. 8. Also, this rung can be represented in VerilogHDL code using "assign" statement as mentioned below.
Application software invokes the parallel event structure as and when the user clicks on the "PARALLEL" control button. In parallel connection, more than one element can be connected in series. Maximum number of elements in series connection must be decided during the design time itself. User has to assign the total number of elements in series, type of the coil and the corresponding name. 'n' case structure can be cascaded for 'n' elements in series. Similarly, successive parallel connections can also be established. Names assigned to each element will be store in memory. Every rung must be ended with an output. Hence VerilogHDL code for the present rung will be generated whenever the output event structure is called. Thus generated code will be stored in memory. Code for the entire LD will be generated when the generate code event structure is called.

Timer
IEC61131-3 standard defines three types of timers namely, Pulse Timer, On-delay Timer and Off-delay Timer [24]. These timers have the input variables IN, Pre-set value (PT), output variables Q and End Time output (ET). Data type of the parameters IN and Q are Boolean. Status of Q is changed based on the Pre-set value of the timer. Delay created by the timer can be read from ET. PLC establishes the function of timer through programming. This work assigns FPGA hardware resources dedicated for every timer included the LD which actually speeds up logic execution [25]. Timing diagrams of all the timers mentioned by the IEC61131-3 has been produced here to have better understanding of the function of timers [24].

Pulse Timer
Pulse timer activates the timer to start counting whenever it detects rising edge of the input IN. Clock pulse of FPGA is used as a pulse generator to the timer. Output Q is set until the count value becomes equal to the value of PT. It is reset once the counter reaches the value of PT and the counting is also stopped. Timer count value is updated to the output ET. It continues to count even when the status of IN is changed to falling edge before the value of PT is reached. Figure 9 shows the timing diagram of a pulse timer.
Description of pulse timer in the form of EDFG is shown in Fig. 10. Rising edge of the input IN activates 'start'. Start is used as s register. This will be reset only when the value of 'tcount' exceeds PT.
'tcount' is used as a counter register. It is reset only when its value is greater than PT and the IN value is low.     output is also inverted before connecting to Q. This ensures that the diagram satisfies the functionality of off delay timer.
LabVIEW invokes timer event structure whenever the "TIMER" control button is clicked. User can choose any one of three timers. By selecting any type of timer, user has to enter the value of preset time. Clock frequency of the FPGA will be known only at the time of implementing the design into an FPGA. Therefore, the user has to identify the clock frequency of FPGA while developing the LD and calculate the count value required to create delay in terms of nano seconds. This count value must be entered whenever timer is used in the design to create delay in the operation. Thus the delay time is accepted in the units of nano seconds by the application software. Timer event structure is responsible to draw the symbol of timer and assigns suitable name to it. The application software moves to the next rung after drawing the symbol of timer. Timer output is assigned to a register variable. Programmer can use this variable in LD to create a suitable logic. Application software has used 'x' as the timer variable. LD can have more than one timer. Hence a numeric index is concatenated with the variable '× '. For example, if there are two timers in the LD, then the first timer will be assigned as ' × 0' and the second timer will be assigned as ' × 1'.

Application Software Design, VerilogHDL Code Generation
Application software design was divided into two parts. One part is responsible to create a graphical display of LD. It also displays the names given to a particular element and stores them in an array. Second part of the software uses this array content to generate VerilogHDL code. Application software generates the code as and when an LD element is placed and stored in an array. It expects the user to do the below actions. Upon the selection of "New" control button, the content of 2D picture indicator will be deleted. A horizontal line will be drawn to indicate the beginning of a first rung. "Series", "Parallel" control buttons are used to place the selected element (NO/NC) either in series or parallel connection respectively. User is requested to assign a suitable name corresponding to the chosen element. "Timer" control button shall be invoked to include the timer in the LD. Time delay must be entered in the unit of nano seconds. Every rung must be ended with an output. Therefore, a rung will be completed only when the ""Output" control button is chosen.
Upon the "Output" selection, symbol for output will be drawn and the next rung will be started. LabVIEW code to draw NO, NC, output and timer elements have been defined as a sub vi. Particular sub vi will be called to draw the symbol based on selection. "Generate code" control button is used to generate Verilog HDL code for the LD developed by the user. This work has utilized RTL level descriptions, especially "assign" instruction. Statement content is generated in association with the LD drawn by the user.

Series Connection-NO/NC Coil
A case structure function inside "series" event structure function will generate VerilogHDL code for this condition. Since the output of NO coil follows its input, name assigned to it is entered as an input variable. Series connection represents logical AND operation. Hence, the symbol for AND operation in VerilogHDL code "&" is added with the element's name. If the coil type is NC, then the input must be inverted. Therefore, symbol for invert operation in VerilogHDL code " ~ " and "&" symbol for AND operation are added before and after the name respectively. Thus generated part of the statement is stored in an array.

Parallel Connection
A cascaded case structure function inside "parallel" event structure function will generate VerilogHDL code for the elements connected in parallel. NO / NC coil shall be connected in series in the parallel connection. This application has limited the maximum number of elements that can be connected to three (In the combination of NO / NC). Dialog window displayed expects the user to fill the details of starting and end point of parallel connection and the NO / NC specification. Number of elements connected in series can be further extended. One case structure function must be cascaded for every addition of an element. Parallel connection indicates the logical OR operation. Symbol for OR operation in Ver-ilogHDL code is "|". This will be included whenever the parallel event structure is invoked. "&" symbol will be included for every element connected in series.

Timer
Timers that shall be included in the LD are pulse timer, on delay timer and off delay timer [24]. Application software is able to generate Verilog HDL description for these timers.

Pulse Timer
Functionality of pulse timer has been already explained in the Sect. 2.1.3.1. Based on the requirements of IEC 61,131-3, Verilog HDL code that will be generated by the application software for this timer is listed below. Input and output variables in, pt, q, et declared in this design are similar to those variables declared by IEC61131-3. This same convention is followed for the remaining timers also.
User enters the delay time to the input variable PT. 'count' is declared as a 32-bit counter with an initial value of zero. Separate hardware must be assigned for each timer to ensure concurrent execution. Hence, the timer index value will be concatenated with the timer counter register 'tcount' and the timer output register 'x'. Variable 'in' triggers the single bit register 'start' to ensure that the timer is activated. 's' register is reset as and when the input of 'in' goes low.

On Delay Timer
On delay timer is started whenever its input is "high". If the 'in' input is changed from the state of "high" to "low" then the timer value will be reset to zero. Timer output will be changed from the state of "low" to "high" only when the timer value becomes equal to the value set by the user. Counter value is reset whenever 'in' input is low. Application software generates the below Verilog HDL code when this on-delay timer is used in LD.

Off Delay Timer
Output of off delay timer is the inverse of its input after the timer reaches the time delay specified by the user. It will be started only when the 'in' input is low. Thus the default status of timer output 'q' is defined to be high. It is changed to low when the count value 'count' reaches the value of 'pt'. VerilogHDL code generated by the application software for this type of timer is shown below.

Output Coil
Selecting an output element indicates the end of rung. Therefore the application software draws the symbol for output and moves the cursor for next rung. It also generates Ver-ilogHDL code as and when one rung is completed. Actually, LD allows an output to use as an input in any rung. "inout" allows a defined variable to be used as either input or output. Hence, by default, all the outputs are declared as "inout". Based on the logic, same input or output may be used in more than one rung. This creates the duplication of input or output during VerilogHDL code generation. Multiple declaration leads to synthesis error. Hence, the multiple usages are identified and only one variable is stored in memory for VerilogHDL code generation. After the generation of VerilogHDL code for the current rung, all the memory elements are initialized to default value.
Complete LD developed using application software can be viewed in the front panel as shown in Fig. 15. Various dialog boxes invoked by the click of control buttons are also shown. VerilogHDL code for the entire LD is developed when the "code generate" event structure is chosen as listed below.
• Form the module name.
• Retrieve all the inputs and outputs. • Declare inputs and outputs (all the outputs will be declared as inout). • Read the individual rungs and concatenate. • Retrieve the VerilogHDL code generated for timer(s). • Mention the "endmodule" statement. • Concatenate all the lines developed using the above steps.
• Store the VerilogHDL code in a text file. Now this file can be copied and used for synthesis and FPGA implementation.

Case Study and FPGA Implementation
Two simple case studies have been presented to verify the functionalities of the application software. They are, • Substances mixing. • Traffic light control system.
Case study of substances mixing has not used any of the output elements as inputs. Thus the design of LD is converted into a combinational circuit. Design of traffic light controller has used both the on-delay timer and off-delay timer. Also, the outputs of one signal are used as an input for the other. Thus the design of LD for traffic light controller has used sequential circuit.

Mixing of Substances
Let an automated process in which water is mixed with two or more substances. Process tank has two level sensor limit switches fixed. One is fixed at the bottom of the tank to indicate low water level (LLLS) while the other is fixed at the top of the tank to indicate high water level (HLLS). Whenever, LLLS output is low, control valve (CV1) opens and hence water enters into the tank. At the same time, a motor is also switched ON to mix the substances with water. This process continues till HLLS output becomes high. A high output in HLLS closes CV1 and switches OFF the motor. Now, control valve (CV2) at the bottom of the tank is opened to empty the tank. It will be closed once the output of LLLS is low. Above mentioned problem is drawn as LD as in Fig. 16. VerilogHDL code was generated by the activation of "generate code" control button click. Thus generated code was stored as a text file in a location as mentioned in the program. Figure 17 shows the RTL schematic of the code generated during synthesis. Unlike LD execution by a PLC, RTL logic generates output as and when there are changes in the inputs. Also, RTL schematic shows individual logic gates for each rung. At this stage, there is no logic optimization. In synthesis process, Technological schematic will be generated after RTL schematic generation. Synthesis software, generates the required hardware resources after optimizing the RTL logic as in Fig. 18.
Rung 1 and rung 2 in LD are similar except that the outputs are different. Even though RTL schematic assigned two separate logic gates to perform similar functionalities, synthesize software is intelligent enough to identify this and assign two different outputs from the 1 3

Traffic Light Control System
Design of traffic light controller has been one of the popular applications. This work has considered this application to prove that the application software is able to generate Ver-ilogHDL code for sequential circuits also. LD was developed for two alternate sequences of traffic light control. In the first sequence, traffic is allowed to in the directions of north and south. At the same time, traffic in the directions of east and west are stopped. Now, the traffic conditions are reversed in the second sequence. The sequence is again started from the first sequence. Figure 19 shows the LD developed using the application software for traffic light control system. Switching sequence of light is as below.
• Red colour light to yellow colour light. • Yellow colour light to green colour light. • Green colour light to red colour light. Delay value between the sequences is entered as 2,00,000 to create the delay of 4 s.

FPGA Implementation
It is easy to implement the VerilogHDL code into FPGA by following a set of predefined procedures. It demands the conversion of VerilogHDL code into a bit file. It is compulsory to assign each NO / NC coil in the LD to FPGA pins as an input or output. In other words, VerilogHDL code expects that the user assigns inputs and outputs to FPGAs to the variables declared in the module [26]. Details of the pin assignment are available in user constraint file (UCF). FPGA vendor assigns suitable names to FPGA pins and by referring these details, one can assign variables to FPGA pins. Synthesis software uses VerilogHDL code and UCF file to generate FPGA downloadable file in the bit format. Joint test action group (JTAG) interface between the computer and FPGA board helps to download the bit file into FPGA. After downloading, FPGA acts as a standalone device. Table 4 lists the inputs and outputs required for this problem.  Table 4 Descriptions and functions of inputs and outputs for mixing osubstances Sl.no Output Will be opened when the tank level is high and closed when it is low 1 3

Data Acquisition System
In industries, a computer in a centralized place gets analog and digital signals from the field instruments. Software in that computer reads the signals and displays the actual process condition [27]. This facility is necessary to ensure safety in process, quality product. It is possible to generate control signals from the computer and changes the process condition. Such a kind of set up is known data acquisition system (DAS). In industrial automation, PLC acts as a mediator between computer and field instruments [28]. It takes a specific time period for data transfer. PLC scan time is inclusive of this time also.
Actually, this is an extra load to PLC. In the proposed design, a portion of FPGA hardware resources takes care of data transfer between FPGA and computer. FPGA is responsible to acquire signals from the field. This guarantees independent operation of logic execution of acquired signals from the field and data transfer to the computer. Figure 20 shows FPGA implementation of case study for mixing of substances. DAS program in the computer displays details of inputs and outputs. RS 232 communication establishes serial data transfer between FPGA and computer. Many process industries and research laboratories use LabVIEW to develop DAS system [22]. Figure 21 shows LabVIEW code for both serial data communication and DAS system.
Following parameters must be similar on both the sides of a system to establish serial data transfer.
Speed of data transfer depends on the baud rate. It will be more when the baud rate is high. However, establishment of high speed communication reduces cable length. Fig. 20 FPGA implementation of case study and its data acquisition system 1 3 LabVIEW software was used on the system end to receive data from FPGA. It reads data sent by FPGA as a string. String to byte array function converts string data into Boolean.

Serial communication-FPGA side
VerilogHDL code for serial communication involves baud rate generation, converting parallel data into serial using shift register and start sending the serial bits one by one till transmit bit is set. Baud rate represents the number of bits sent per second. There is a relationship between baud rate and FPGA clock pulse. Dividing FPGA clock pulses for a predetermined count decides the baud rate. Therefore, a comparator compares the counter value with predetermined number of clock pulses.
Counter increases its count for every clock pulse. Since the computer does not generate any control signals to FPGA, VerilogHDL code was generated for transmitter alone. RTL schematic of DAS in Fig. 22 shows that FPGA allocates separate hardware for logic execution and serial communication. Figure 23 shows DAS system of traffic light control system.

Results & Discussions
Main focus of this work is to develop a feasible solution for the generation of VerilogHDL code equivalent to the LD. In addition to that, it also focused on the following functionalities to verify the design and provide a diagnosis system.
• Case study for the conversion and its FPGA implementation • Data acquisition system of FPGA    Table 6 shows the delay time of various FPGAs to execute the logic for both the case studies. In traffic light control system, the design has used four simple on-delay timers and two off-delay timers. All these six timers will be functioning concurrently. PLC cannot activate more than one timer at a time. Thus, FPGA implementation helps to develop better quality product.

Comparison of Case Study-PLC and FPGA
Proposed design has attempted to realize LD in terms of VerilogHDL code. Because, FPGA has been a better alternative for PLC [29]. Hence, the proposed work has compared the performance of FPGA with PLC. GE Fenauc Series 90-30 35 × Micro PLC has been considered for the purpose of performance comparison. The case study of substances mixing utilizes five inputs and three outputs. Scan time of five discrete inputs is 0.15 ms as the scan time for one discrete input is 0.03 ms [30]. Similarly, the scan time for three discrete outputs is 0.09 ms. Hence the total scan time for five inputs and three outputs are 0.24 ms. Delay time of XC3S200 FPGA identified from Table 6 is 9.558 ns only. This time is inclusive of the scan time of input and output signals and the time required for the execution of logic. This comparison has not included the time required for housekeeping, program execution, programmer service and the system communication. This increases the PLC sweep time. Also, if the PLC is programmed for other applications in addition to the case study, then the PLC sweep time is increased further. This indicates that the PLC sweep time solely depends on the total number of rungs, inputs and outputs used in the LD and hence it is not constant. In the same way, FPGA can also be programmed for other applications in addition to the case study. In this case, the execution time remains constant as the hardware resources of FPGA for the case study and other applications are separate.
Apart from the time calculation, presented case studies can be viewed in the perspectives of quality of process operation. Case study of substances mixing involves mechanical parts whose response time will be in milliseconds. PLC may miss to identify and hence response to the changes, if it happens in between the sweep time of PLC. Whereas, FPGA will definitely identify the changes as its execution time is 9.558 ns. However, if the changes happen in the time of less than 9.558 ns then the FPGA also will miss to identify the changes. Thus the comparison proves that the FPGA is best suitable for high speed applications than that of the PLC.
Adding more number of digital inputs/outputs to the PLC increases its scan time. Digital input / output modules have in-built processors to handle these inputs / outputs. FPGA has both inputs and outputs and it provides the flexibility of treating input as output and vice-versa. PLC communicates to separate modules to receive digital inputs and send digital outputs. Table 5 shows that the device XC5VLX330T has 960 I/Os, whereas modules connected with PLC has the capacity of maximum of 64 inputs or

Conclusion
Case & event structure in LabVIEW, "assign" statement in VerilogHDL code are sufficient to create equivalent VerilogHDL code for the given LD. However, software package provided by PLC vendors to develop LD has numerous functional blocks. In VerilogHDL code, these functional blocks can be developed as library functions. Those library functions can be invoked as and when they are used in a LD. In this way, LD development using LabVIEW will become a complete solution for VerilogHDL code generation.

Authors' Contributions
All authors contributed to the study conception and design, material preparation, data collection and analysis were performed by GD and STS The first draft of the manuscript was written by GD and all authors commented on previous version of the manuscript. All authors read and approved the final manuscript.
Funding All authors certify that they have no affiliations with or involvement in any organization or entity with any financial interest or non-financial interest in the subject matter or materials discussed in this manuscript.
Code Availability (software application or custom code) The code generated during the current study is not publicly available but are available from the corresponding author on reasonable request. The code generated during the current study is not publicly available but are available from the corresponding author on reasonable request.

Conflicts of interest
The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this manuscript.