Design of HeterojunctionTunnel Field-Effect Transistors with SiO2 isolation between Source and Drain for Low Power Application

— This paper presents a numerically simulated Ge-source based Tunnel Field Effect Transistor with (TFETs) SiO 2 segregation between the channel and drain. The developed device has been compared with conventional TFET and without isolated heterojunction TFET. The use of oxide segregation between channel and drain enhances the performance of the device in terms of ON-state current as well as subthreshold swing (SS). The electrical characteristics such as surface potential, electric field, transfer characteristics, output characteristics of the proposed device have been studied. The temperature variation of the proposed device has also been studied. The proposed device offers high ON current of 3x10 4 A, I ON /I OFF ratio of ~10 11, and enhanced SS of 30 mV/dec. The validity of the proposed device has been done by Synopsys Sentaurus TCAD.


I. INTRODUCTION
The escalation of technologies and the rising miniaturization of electronic devices like smartphones, tablets, sensor networks, etc., has been making Internet of Things (IoT) an important innovation in the current scenario of an information-based society. IoT connects everything and makes daily lives better, and becomes essential for the future of the world.
Some of the facets that are particularly relevant to explain the acceleration of IoT technologies, i.e., the dimension of the devices, ability of the device to be integrated in the real world, the ability of the device for computational and memory capacities, etc. On that account, the development of device technologies is necessary to get the final objective of real and big-scale IoT applications [1][2]. The low power specially low stand-by power is the most essential requirement for devices in IoT application [3].
Among various emerging devices, TFETs, based on the band-to-band tunneling (BTBT) mechanism,have proven to be promosing devicein terms of lower OFF current, SS below 60 mV/dec, unsusceptible toward SCEs, and suiltable for low power high speed switching devices [13][14].TFET has a significant issue of low ON than conventional MOSFETs current [15],however, heterojunction TFETshas been widely studied in recent years duw to the possibility of overcoming low ON current, amipolarity, high threshold, etc [16][17][18].
In this work, we proposed a heterojunction TFET with SiO2 isolation between source and drain of gate length 50 nm at V DS = 0.4 V. The proposed device is compared with conventional TFET and Ge-source TFET without isolation. The proposed device offers high ON current of 3x10 4 A, I ON /I OFF ratio of ~10 11, and enhanced SS of 30 mV/dec, respectively.
The impact of temprature has also been studied to show the reliability of the reported device.

II. TUNNEL FIELD EFFECT TRANSISTOR
In this section, the basic overview of TFET in terms of the device structure, operating principle, and physics has been discussed. It has already been revealed from various studies that TFET works byinterband tunneling mechanism. The electrons as charge carriers transfer from one energy band into another band at a heavily doped p i n + + − − junction, as shown in In the ON-condition of TFET, the gate voltage ( ) V G carriers are tunnel into the channel throughthe potential barrier, based on BTBT. In the OFF-condition of TFET, the channel barrier is large, so there is no flow of current. Practicality, not zero due to the thermal distribution of carriers, as shown in Fig 1(b). Only the P-I-N diode leakage current flows between the source and drain,and this current can be extremely low [19].

III. HETEROJUNCTION TUNNEL FIELD EFFECT TRANSISTOR
In the past few decades, several researchers have been working for effective gate control and enhancing tunneling probability of heterostructure TFET by using different device engineering such as gate engineering, tunneling barrier engineering, spacer engineering, gate engineering, etc. [7].The fundamental difference between the homojunction and heterojunction TFET, as shown in Fig.2. It is clear from the figure that both homojunction and heterojunction TFET have been designed with asymmetrical doping of the source anddrain so that it acts as reverse-biased gated p-i-n diodes.Keeping these points in mind, our work has been based on heterojunction TFET [20][21]. In this section, the physics of the heterojunction TFET has been discussed and compared with homojunction TFET. T is large and gives low ON current, which is one of the disadvantages of convention TFET, as shown in Fig. 3 (a).The b T has been reduced using heterojunction, which enhances the tunneling current, as shown in Fig. 3(b).

IV. ARCHITECTURE OF PROPOSED DEVICE
The proposed device is a Ge-source based Tunnel field-effect transistor (TFET) with SiO 2 isolation between source and drain. The proposed structure (D1) has been compared with a silicon-based TFET without SiO 2 isolation (D1) and a Ge-source-based structure without SiO 2 isolation (D2), as shown in Fig. 4.
For all the three TFET designs, the source, drain, and channel have been doped with 1e20, 1e19, and 1e15, respectively. The gate length is 50 nm and is made up of polysilicon. The length of source and drain are 20 nm each, respectively. The dielectric is 1nm thick and is made off high-k dielectric named HfO 2 . A box structure made up of SiO 2 is place to provide isolation between source and drain. The problem with a Si-based design was low ON current, ambipolarity, and leakage current. To address these problems, the source has been replaced with germanium as it has higher ON current, as well as less ambipolarity.The various optimized parameters used for the proposd device are listed in the Table I  First of all, the TCAD simulation data of the reported device have been calibrated against the experimental data of reference [21] at drain voltage0.5V as shown in Fig. 5. It is observed that there is a good matching of both data, which certifiy the validity of the selected models.
In this part ofThe comparison between all the devices D1, D2, and D3 has been made at fixed V DS = 0.4 V, as shown in Fig. 6

V. PROPOSED TUNNEL FET PROCESS STEPS
The proposed Ge-source-based TFETwith SiO 2 segregation may be fabricated on a lightly doped p-type SOI wafer, as shown in Fig. 7. The following steps have been required for the possible fabrication of the proposed device.
• Thermal Oxidation: This technique has been used to scale downthe SOI layer to 15 nm and then remove the grown oxide. The optical lithography and dry etchinghave been used to pattern the active area [21], as shown in Fig.7(a).
• Ion Implantation and Thermal Annealing:Ion implantation technique has been used for masking, whereasthermal annealing has been used for heavy n-type impurity doping in the drain region [21]. • Isotropic Dry Etching: This process has been used to recess silicon in the source area undercutting the gate electrode, as shown in Fig. 7 (c).

• Low Pressure Chemical Vapour Deposition: This Low Pressure Chemical Vapour
Deposition (LPCVD) rector has been used todeposit the boron doped germanium. To permit direct probing of the gate, source, and drain pads, an additional patterned and etched LTO layer has been deposit. At last, the gas annealing has been used to enhance contact resistance as well as the properties of the interface [22], as shown in Fig. 7(d).

VI. RESULTS AND DISCUSSION
This section has discussed and validated the proposed device's resultusing the Synopsys  In Here, the surface potential is calculated by the potential along with channel of the device at the Si-SiO 2 interface and the potential is computed in respect of source Fermi level. Fig.9 shows the electric field variation from source to drain region for different gate voltages.
In the ON condition of the device, the source doping will enhance the energy bands in source region and this decreases the tunneling barriers for electron as charge carrier to tunnel to the drain region. The increase in the electric field is observed due to a steep transition between energies of channel and source region. It is observed from figure that as the gate voltage increases the electric field at the source-channel junction also increase due to the maximum number of charge carriers to tunnel through the junction [24].      Fig. 11. The tunneling barrier decrease as the gate voltage increase and this enhance the drain current due to large number of electron passes from source region to channel region. The transfer characteristics for different dielectric materials is shown in Fig. 12 The drain current vs gate voltage for different temperatures is shown in Fig. 12. It will clear from the energy gap equation as it is the function of temperature and is given by [26][27][28][29][30].
where, γ ( 4.7 x 10 4 eV/K) and β (235 K) are the fitting parameters for Ge. It is clear from the above equation that the energy gap depends on temperature. The drain current depends on the energy gap, so it also depends on temperature. The slight increase in ON current and SS has been shown in the figure. It is noticeable from the plot that OFF current increases for temperature variation, but it is below the ITRS requirement.

VII. CONCLUSIONS
In this work, a numerically simulated Ge-source-based TFET with SiO 2 segregation between channel and drain has been investigated for the low power applications. The analyzed device has been compared with conventional TFET and heterojunction TFET without segregation between channel and drain. The use of segregation amplifies the performance of the proposed device in terms of ON current, OFF current, SS and ambipolarity.The proposed device has also been analyzed with temperature variation. The proposed device has been validated by Silvaco Synopsys TCAD.The proposed device is a low power device and it is suitable candidate for low power digital applications. Moreover, in the current scenario of an information-based society, it can be used for Internet of Things (IoT) application.