Drain-Engineered Reconfigurable Transistor Exhibiting Complementary Operation

In this paper, we propose and simulate a multifunctional transistor that exhibits device reconfigurability and realizes both nFET and pFET electrical characteristics when adequately biased. The use of this device will significantly reduce the transistor count in realizing sequential and combinational circuits and will result in highly compact design. The device uses a dual fin structure having a single mid-gap workfunction gate (∼\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$\sim $\end{document}4.65 eV) alongside dual metal (metal-silicide) drain regions. It employs n+/p+-i junctions at the source-channel interface along with the Schottky junctions at the channel-drain interface. In practice, metal-silicides such as erbium/ytterbium silicide (ErSix/YbSix) for the n-drain and platinum silicide (PtSi) for the p-drain can be used as they provide smallest electron and hole Schottky-barrier heights (SBHs). Simulations carried out using calibrated parameters show better drive current (≈ 10− 2 − 10− 3A/μ m) compared to the quantum tunneling current in simulated state-of-the-art multifunctional devices (≈ 10− 4 − 10− 5A/μ m). In addition, butterfly curves show symmetric high (NMH) and low (NML) noise margins of 0.43V and 0.29V for zero and finite SBHs, respectively. The switching characteristics is shown to have an overshoot of ∼\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$\sim $\end{document}0.15 V for realistic SBHs which is then eliminated for the case of zero SBHs. In the last section, it is also demonstrated that a simplified structure having single mid-gap workfunction (∼\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$\sim $\end{document}4.65 eV) drain of Nickel silicide (NiSi) does not hamper the reconfigurability of the device.


Introduction
For the past four decades, the primary technique used in the VLSI industry to keep Moore's law valid is the aggressive scaling of the MOSFET physical dimensions. This so far has resulted in high level of device integration and has given rise to integrated circuits (IC's) with high speed and density [1,2]. However, as CMOS dimensions have entered into the nanometer regime, the ever-increasing short-channel effects (SCEs) along with the unscalable subthreshold slope (SS ∼ 60mV/dec) limit of the MOSFET [2], and similar current transport devices [3,4], has resulted in a rapid rise in the leakage current. This increases the standby power consumption significantly, and in consequence, has imposed the limit on transistor integration alongside the switching speed [5].
Steered by the need to overcome the aforementioned limitations, various advanced device geometries including FD SOIs [3], III-V MOSFETs [5], FinFETs [6], nanowire FETs [7] have been proposed in the literature. Alternate current transport devices based on Schottky barrier tunneling based dopant-segregated ultrathin-body MOSFET [8,9], band-to-band tunneling (BTBT) such as silicon based lateral/line Tunnel FETs [10][11][12], graphene based TFET [13], negative capacitance (NC) based nanowire TFETs [14] and junctionless FET [15] alongside electrostaticallydoped source-drain TFETs [16] have also been explored. In addition, to overcome the doping limitations, DG architecture based on charge plasma concept [17], nanowire (NW) and nanosheet (NS) junctioless FETs [18][19][20] have also been heavily investigated. All these geometries have so far focused on achieving the increased performance out of the individual device unit alongside supply voltage (V DD ) scaling, whereas a few handful of them have tried to increase the device functionality instead [21][22][23]. In this regard, Si NWs based reconfigurable transistor that can be programmed dynamically by an external voltage were fabricated [24]. The NWs are undoped and are controlled by a dual Schottky junctions at the source-channel and channel-drain ends. In consequence, carrier injection (holes for pFET and electrons for nFET) can be modulated by keeping one gate voltage constant and other variable. Another device fabricated that exhibit reconfigurability is a vertically-stacked (VS) Si Gate-all-around (GAA) NW FET having controlgate (CG) and polarity-gate(PG) [25]. PG is kept constant which determines the mode and CG acts as a conventional gate in that particular mode. Earlier, a complementary device using a double-gate (DG) architecture based on a Schottky-barrier (SB) tunneling has also been demonstrated via simulations [22]; however, it has certain downsides: 1) the inherently low drive current associated with the SB FET; 2) the need of two individually tuned gate workfunctions for optimum device functionality; 3) the leakage due to the coupling between non-isolating channels during the pFET and nFET operation. Other than this, in terms of fabrication, complementary operation in a single device so far reported [22,[24][25][26][27] have been at the cost of high operating voltages (V DD of ∼ 3−4V).
Most of the complementary devices are based on the Schottky tunneling based current injection mechanism; however, they inherently suffer from low drive current compared to conventional FET. To understand the reason for this, we revisited the fundamentals. For a silicide source, the emitted current density J s is composed mainly of two components, i.e., the thermal emission J th and the current due to quantum mechanical tunneling through the Schottky barrier J fe (thermionic field-emission and field-emission current are clubbed together here for simplicity). At small V (gate voltage), J s equals J th ; however in the ON-state, when there is a high field, J s is mainly dominated by the J fe . So, unlike the conventional FET wherein current is controlled by the thermal-emission barrier in the channel, current in SB FET is limited by the tunneling barrier at the source [28][29][30]. For this reason, a low current drivability in SB FET is observed.
Keeping in view the above drawbacks, in this paper, a transistor exhibiting device reconfigurability is proposed and simulated and can also be biased in the inverter mode. The veracity of the complementary switching mechanism is envisaged using a dual fin design having doped n/p sources and metal (metal-silicide) as drains. The device is being termed as a Drain-Engineered Reconfigurable FET (DE RFET) due to the connected metal (metal-silicide) drains. It overcomes the low drive current originating from the quantum tunneling current J fe , as present in the silicide-source SB FET architecture [22]. Additionally, the wrap-around gate architecture facilitates the path to volume inversion compared to that of a thin inversion layer in DG architecture.
Recently, we have also proposed a vertically stacked dual drain exhibiting reconfigurability [31] but its junctionless behavior demands complex doping strategy, and therefore, dual fin design mitigates this to some extent. The present work employs single gate and differs from [31] as it has double gate architecture. In addition, in the present work, the choice of single silicide drain having midgap workfunctin to simplify the device architecture is also proposed in the last section. and P-source (acceptor N A = 1×10 20 cm −3 ) regions. Two silicon fins, controlled by a single gate, will contribute individually to the n/p sections of the device operation. Both the sections have an extended undoped channel length of L ext . In addition, dual-connected n/p silicide drains of suitable workfunction, φ Dn and φ Dp (or SBH, Dn and Dp ), are used to sink-in the electron and hole currents, respectively, during the n/p FET operations. All other device parameters are provided in the Table 1.

Device Structure
It is an arduous task to come up with a detailed process flow until the device has actually been fabricated. However, key processing possibly include: starting with an SOI wafer, the device island can be patterned with fins [34]. Next, gate dielectric can be thermally grown or deposited. After this, gate metal layer such as titanium nitride (TiN) can be deposited via chemical or plasma vapor deposition (CVD or PVD) and then patterned [35]. Next, silicon nitride gate-sidewalls spacers can be formed [34]. Thereafter, selective deposition of borosilicate glass (BSG) layer and phosphosilicate glass (PSG) layer, respectively, for p-type and n-type doping can be done, followed by the high temperature annealing process [35]. Selective deposition of near band-edge workfunction Pt metal for D2 and Er or Yb metal for D1 can next be done, followed by silicidation to form connected drains. Unreacted metals can be removed using wet chemical etch. Finally, metallization and chemical mechanical polishing (CMP) can be done. Cutlines/Cutplanes AA' and BB' are drawn the fins. Simulation models were calibrated from fabricated the tri-gate SOI JLT [32] by matching the transfer characteristics. In addition, lateral tunneling parameters are taken from [33] to account for the OFF-state leakage (c) [32]

Simulation Methodology
To have a proper Schottky junction at the channel-drain interface, complementary or near band-edge metal-silicides are required. The choice of workfunctions for the same are as follows :φ Dn < φ Si < φ Dp where φ Si = χ Si + E g /2, is the undoped silicon workfunction; χ Si is the electron affinity (4.05eV), φ Dn and φ Dp are n/p metal drain workfunctions and E g is the bandgap of bulk silicon (1.12eV). φ Dn < φ Si [36,37] provides no barrier to electron flow but creates barrier for hole diffusion from silicon to metal (metal-silicide). Similarly, φ Dp > φ Si [36,37] provides no barrier to hole flow but creates barrier for electron diffusion from silicon to metal (metal-silicide). In practice, near band-edge metalsilicides such as erbium silicide ErSi x or ytterbium silicide YbSi x ( Dn ∼ 0.27−0.36eV for electrons) [37,38] for the n-drain (D1) and nickel or platinum silicide ( Dp ∼ 0.15−0.27eV for holes) [37,38] for the n-drain (D2) can be used. Here, Dn and Dp are, respectively, the smallest electron and hole SBH reported with the silicon, [38]. Ideally, the SBH Dn and Dp equals (φ Dn − χ Si ) for the n-drain and (E g − φ Dp + χ Si ) for the p-drain, respectively, however, it may vary depending upon the non-idealities. In addition, close to mid-gap workfunction for the gate, corresponding to the TiN metal [39] (∼4.6-4.9eV), is chosen.
All 3-D simulations were performed on the Synopsys Sentaurus TCAD [40]. Various models invoked in the simulations are Philips unified mobility model that takes into account the concentration dependent mobility along with its degradation due to both impurity and carrier-carrier scattering. In addition, Bandgap narrowing model (BGN) due to the highly doped n/p source, Shockley-Read-Hall (SRH) and Auger recombination models are also invoked. Fermi statistics is utilized in conjunction with the driftdiffusion physics. As indicated in the Fig. 1(c), simulation models were first calibrated by reproducing the transfer characteristics and matching it with the tri-gate SOI JLT [32]. To account for the lateral tunneling dominant in the OFF-state, nonlocal BTBT model calibrated from the [11,33,40] is activated. Besides, carrier confinement due to the quantization effect is taken care of using the modified local density approximation (MLDA) model. nFET operation, with V G = V DD , a path for electron flow between the n-source (S1) and n-drain (D1) is created. Figure 2(c) and (d) shows the I D -V G characteristics for the pFET obtained by biasing the V S2 to V DD , V D to 0V, and sweeping the V G from 0V to V DD . Similarly, for nFET, I D -V G characteristics are obtained by biasing V S2 to V DD , V D to V DD , with V G being swept from 0V to V DD . Further, in addition, Fig. 2(e) and (f) shows the I D -V G characteristics for two different L ext values of 5nm and 20nm at a fixed gate workfunction, φ G of 4.65eV. We observe that reducing the L ext increases the OFF-state current. This occurs due to the band overlap between the channel valence band (VB) and the drain conduction band (CB) during the OFF-state, which in turn, results in lateral tunneling of charge carriers. D2   which then is eliminated with the applied gate bias in the ON-state. Note that the n-section during the pFET operation remains in equilibrium and remains inactive. Similarly, during nFET as shown in the Fig. 3(c) and (d), p-section fin remains inactive and the other fin contribute to the conduction with the proper gate bias. Here, E fn and E fp represent the fermi-level in the n-drain (D1) and p-drain (D2) regions, respectively.

OFF-State Leakage During n/p FET Operation
Further, to understand the reason for the OFF-state leakage, Fig. 4(a) shows the nFET OFF-state 2-D hole generation rate showing the increased lateral tunneling at smaller L ext of 5nm, verifying the increased leakage in the OFF-state, shown in the Fig. 2(e) and (f). In nFET, carriers tunneling constitutes of the holes moving from the metallic drain region (D1) and CB of the underlap region into the channel VB. As shown in the Fig. 4(b), we also observe the tunneling during pFET operation for φ G = 4.65eV at reduced L ext = 5nm. This is due to the sufficient band bending across the channel/drain region during the pFET operation, which results in the tunneling of electrons from the metallic drain region (D2) and CB of the underlap region into the channel VB.

Output, VTC and Transient Characteristics
The output characteristics corresponding to the n/p FET configurations are shown in Fig. 6(a). The pFET drain current flows between the terminal D2 and S2, denoted by I DS2 and corresponding, nFET drain current flows between the terminal D1 and S1, denoted by I DS1 . A reasonable output characteristics with good saturation are obtained for both the modes. As depicted in Fig. 6(b), when DE RFET is configured as as an inverter unit with biasing scheme shown as an inset in the figure, a reasonable symmetric VTC curve with good high and low logic levels (V OH and V OL ) were   (d) obtained at V DD =1V. The reason is the matched n/p FET characteristics obtained with the gate workfunction tuning, φ G to 4.65eV (slight ON-current mismatch occurs due to the mobility difference between the holes and electrons).
However, φ G of 4.75eV adversely shifts the cross-over n/p FET voltage close to 0.6V, as illustrated in the Fig. 6(c). This will, in turn, result in the asymmetric noise margins (NM H > NM L ), which was reduced by an optimum φ G of 4.65eV. A slight mismatch in n/p FET ON-currents still persists; however, VTC curve remains close to symmetric, implying equal high and low noise margins. We have also shown the impact of the V DD scaling on the VTC curve upto 0.6V. DE RFET design offers the possibility of scaling the V DD without much degradation in the VTC. Further, Fig. 6(d) shows the transient analysis of the DE RFET when subjected to a ramp input pulse of 1V peak-voltage with rise time: t r = 1ps, fall time: t f = 1ps and on time: t on = 50ps. A close to CMOS-like switching characteristics with minimal rise/fall propagation delay is achieved using only a single device.

Impact of Device Parameter Scaling on Reconfigurability
With recent trends moving towards the device scaling, it is essential to explore its impact on the device performance. In this regard, Fig. 7(a)-(c) compares the impact of gate length, L g , fin width, W f in and fin height, H f in scaling upon the reconfigurability of the DE RFET. We observe a significant deterioration in the ON/OFF ratio at L g = 20nm compared to that at 50nm, both for the nFET (≈ 10 6 ) and the pFET (≈ 10 4 ) operation of the device. This is due to the increased short-channel-effects (SCEs) causing reduced gate controllability at short gate lengths. This can be mitigated by reducing the fin width alongside the use of smaller EOT of 0.5nm. We further observe that increasing the fin height increases the ON-current of the device without much degradation in the OFF-state current. Similar observation is also made for the fin width. With reduction in the W f in , tight gate control results in better subthreshold slope. Despite all these variations, the reconfigurability aspect of the DE RFET remains intact with reasonable deviations in the device parameters. Further, Fig. 7(d) explores the plausibility of using the proposed DE RFET as the supply voltage, V DD is scaled. The device works reasonably well in the inverter mode up to the V DD of 0.6V.
Moreover, DE RFET, as a reconfigurable device has also been compared with the existing literature, as listed in the Table 2. The device is comparable in terms of performance with the window for further reducing the operating voltage.

Impact of Finite SBH
So far we have taken D1 and D2 workfunctions as such that the effective SBH is close to zero. However, in practice the SBHs are not negligible rather it has a finite value. Therefore, here we set the electron SBH for D1: Dn ≈ 0.28eV, corresponding to the erbium silicide ErSi x and hole SBH for D2: Dp ≈ 0.15eV, corresponding to the platinum silicide PtSi. We then observe in the Fig. 8(a) that the VTC curve is slightly degraded due to the increased barrier resistance existing at the channel-drain junctions. To assess and evaluate the noise margin, we have considered two conidtions, as indicated in the Fig. 8(b) and (c): 1) VTC with ideally zero SBHs and 2) VTC with finite SBHs. In both cases we have drawn butterfly curves and calculated the high and low noise margins, NM H and NM L . For the Equal noise margin indicates that the VTC is close to symmetric. Further, in Fig. 8(d), the impact of finite SBHs on the inverter characteristics is analyzed. We observe increased overshoot voltage alongside increased output delay in comparison to the zero SBH case shown in the Fig. 7(d).

Impact of Single Mid-Gap Silicide on Reconfigurability
In this section, a new device architecture having a single silicide as a drain region is analyzed instead of two near band edge silicides, as shown in the Fig. 9(a). A midgap drain silicide (NiSi) corresponding to the workfunction of 4.65eV is used. We observe marginal decrement in the ON-state current during both modes of operation. This occurs due to the increase in SB height at the channeldrain junction of both the fins. Further, it is noteworthy that the mid-gap silicide also increases the lateral tunneling of carriers during the OFF-state. The use of single drain silicide, however, does not hamper the reconfigurability and we observe good I D -V G characteristics, as shown in the Fig. 9(b) and (c). Finally, we can infer that the proposed concept is generic in nature, and therefore can be further extended to other device geometries or alternate current transport devices.

Conclusion
In summary, using 3-D mixed-mode simulations, a new device concept, DE RFET, is proposed and investigated. The device can be reprogrammed as an n-type, p-type FET and a complete inverter unit with adequate biasing. The use of single mid-gap silicide or connected dual near band-edge metal (metal-silicide) drains envisage the complementary switching action. Insights into the device operation reveals device reconfigurability, CMOS-like inverter action with a window for future V DD scaling.