Modeling and design of a Mott selector for a ReRAM-based non-volatile memory cell in a crossbar architecture

In this work, we developed a model for a nonvolatile memory cell based on the electrical model for a TiOX/HfOx ReRAM cell and the hybrid electrothermal model of a VO2 Mott selector developed recently by our team. Both models have been calibrated and validated with experimental data, and the operating characteristics of a one-selector-one-ReRAM (1S1R) memory cell has been studied. The length of the selector layer was varied as a design parameter to meet the design requirements for proper read, write, and erase operations. Simulation results suggest that the modified selector cell with 60 nm length of the VO2 layer meets all the requirements for proper operation, with a cell write voltage of 1.6 V and erase voltage of 2.5 V. The access time for this structure was studied by benchmarking with experimental data. Write access time of 10.5 ns and erase access time of 16 ns have been obtained from simulations.


Introduction
Resistive random access memory (ReRAM) is a competitive candidate for the next generation of nonvolatile memory (NVM) devices due to its excellent scalability, fast switching speed, simple device fabrication, and twoterminal structure.This device has the potential for use in a three-dimensional (3D)-stacked memory architecture [1][2][3][4][5].It has also received significant attention for neurocomputing hardware due to nonlinear characteristics which can emulate the spike signal communicated between neurons [6][7][8].Conversely, the crossbar architecture provides great potential for high-density ReRAM array implementation, in which the cell size could be as small as 4F 2 (F is the minimum feature size) [9].However, the crossbar architecture has a significant drawback with pure passive ReRAM cells.Parasitic current paths through neighboring cells, which are referred to as sneak paths, may cause leakage and may alter unselected memory cells during read or write operations [10].A selector device connected in series with the memory element is used to solve the sneak path issue.Various types of selector devices have been proposed, including diodes (one-diode-one-resistor [1D1R]), CMOS transistors (one-transistor-one-resistor, [1T1R]) [11], bipolar junction transistors (1BJT1R), or even a second ReRAM cell [12].Among those methods, 1T1R and 1BJT1R involve complex fabrication processes [13] and require a three-terminal device which is not fully compatible with the crossbar structure.Mott devices based on transition metal oxides exhibiting conductivity switching or insulator-to-metal transition (IMT) at room temperature are a promising candidate for selector devices in crossbar architecture, with a switching time on the order of a few nanoseconds.Several studies have investigated the selector properties of vanadium dioxide (VO 2 ) and niobium dioxide (NbO 2 ) as Mott selector devices [14][15][16][17].A Mott selector connected in series with a ReRAM forms a one-selector-one-ReRAM (1S1R) memory cell structure.The device modeling community has tried to develop comprehensive models to accelerate the analysis, design, and development of NVM devices.The ReRAM models have usually aimed to simplify the complex process of ion and vacancy migration and the formation of a single dominant conductive filamentary path [18][19][20][21][22].Among those, the Stanford-PKU compact Verilog-A model [18] is a viable choice to simulate the ReRAM along with other circuit elements [18].For Mott selector modeling, there are two main mechanisms proposed in the literature to explain the IMT: (i) structural changes induced by Joule heating (thermal) [23] and (ii) field-assisted carrier generation (electrical) [24].We recently proposed an analytical hybrid model which takes into account the interaction of both Joule heating and field-assisted transition [25].In this model, the contribution of electric field, temperature, and carrier concentration as main parameters affecting the transition is considered [25].The main advantage of the proposed model is that it can estimate the device characteristics from pure thermal transition to pure electrical transition as the design parameter varies, which is crucial feature for a design-oriented model.
In this paper, we used the proposed model [25] calibrated with an experimental device [26] along with the Stanford-PKU ReRAM model [18] calibrated with experimental data [19] to design a 1S1R NVM cell for crossbar structure.Then we used the proposed model to check the design requirements and make the cell more robust against sneak path leakage.
This paper is arranged as follows: In Section 2, device structures, modeling approaches, and model calibrations for ReRAM and the Mott selector are presented, and design requirements for proper read, write, and erase operations are discussed.Section 3 illustrates simulation results and discusses the improvement of the selector by adjusting the VO 2 layer length to meet the design requirements.Finally, Section 4 concludes the paper.

ReRAM element
Figure 1a shows the schematic cross-section of the ReRAM element, obtained from an experimental report [18], which consists of TiN/TiO X (~ 5 nm)/HfO x (3.3 nm)/Pt.The HfO x is the active ReRAM layer sandwiched between TiO x and the bottom electrode.
The operation of the ReRAM is described by conductive filament (CF) formation as a result of oxygen ion movement, vacancy generation, and recombination events [6].In the Stanford-PKU model [18], a single dominant filament is assumed, and the core variable is the gap size (g) between the filament and the bottom electrode which controls the resistance of the cell.The time derivative of g is related to the oxygen ion activation energy barrier and the applied voltage obtained from the original theory of filament formation as a result of oxygen ion movement and vacancy generation [27]: where V is applied voltage, E a is activation energy for vacancy generation, a 0 is the hopping site distance, t ox is the oxide thickness, k is the Boltzmann constant, T is ambient temperature, and υ 0 is a fitting parameter.According to the proposed model [27], in the absence of an electric field, the probability per second that a particle with the escape rate of may overcome the barrier of E a is proportional to exp(−E a ∕kT) .In the presence of an electric field (F), the height of potential barriers is changed by the amount of +qFa 0 ∕2 toward the field and by −qFa 0 ∕2 in the reverse direction, where a 0 is the distance between adjacent lattice positions (hopping distance).So the probability that ions move in the direction of the field becomes: exp − E a − qa 0 F 2 kT and in the opposite direc- tion, exp − E a + qa 0 F 2 kT .Therefore, the mean velocity of the drift is obtained by the average value of the probabilities leading to a sinh() function similar to Eq. (1).Similar physics leads to Eq. (1), where the gap size between the tip of the filament and the opposite electrode is controlled by the electric field (F = V/t ox ), and a field enhancement factor (r) takes into account the polarizability of the material.Besides, as the current flows, the temperature is updated due to the self-heating effect, and the electric field in the gap region is increased as the gap size decreases.As a result, nonlinear and hysteresis I-V characteristics are observed.Details of model equations are presented in [18].We implemented this model in MATLAB and calibrated it with the experimental device [19] using parameters and constants listed in Table 1.
Figure 2a compares the I-V characteristic for the "Set" (write) operation obtained from the model with the experiments.This result confirms that the model fits very well with the experimental report.Assuming that there is no filament in the structure initially, and the ReRAM is in the insulator phase, the electrical potential applied to the device is increased from 0 to 2.0 V to perform the write operation.The model suggests that the filament is formed entirely around 1.6 V, and a jump in current is observed.In the backward path, the electrical conductivity remains high, which confirms the nonvolatile storage characteristics demonstrated by the model.Figure 2b shows I-V characteristics of the ReRAM during "Reset" (erase) operation obtained by the model and compared with experiments [18].The sweep begins with the device in the "Set" state; the filament is entirely formed inside the device, and the electrical resistance is about 10 KΩ.The voltage is swept from 0 to −2.5 V to perform the erase operation.The filament is removed entirely at −2.5 V, and the electrical resistance jumped to 1 MΩ.A noticeable decrease in electrical current is observed during the backward sweep from 2.5 V to 0. Again, the model shows perfect agreement with experimental data.The slight difference is attributed to the current limiter used in the experimental report.

VO 2 Mott selector
Figure 1b demonstrates the schematic cross-section of the VO 2 Mott layer sandwiched between two electrodes.Experimental implementation of this structure as a Mott selector is reported in [26].We proposed an electrothermal hybrid model in [25], which captures two main mechanisms responsible for Mott transition, (i) Joule heating and (ii) field-assisted carrier generation, in the form of the Poole-Frankel effect.The transport of carriers at the insulating phase of the VO 2 layer is modeled based on the drift-diffusion framework, current continuity equations coupled to the heat transfer equation [28]: where J is the current density, µ is mobility, E is the electric field, D is the diffusion coefficient, r is the recombination rate, g is the generation rate, V is the electrical potential, ρ is the charge density, є, is the electric permittivity, c is the heat capacity, K is the thermal conductivity, T is the temperature, and σ(T) is the temperature-dependent electrical conductivity.Karda et.al [28] proposed using this model along with empirical temperature-dependent bandgap collapse to prepare a semiclassical electrothermal model for the IMT.
However, the proposed model does not take into account the Poole-Frankel effect, which occurs only in an electric field beyond 10 5 to 10 6 V/cm, which is unattainable in normal planar structures but is the dominant effect in a Mott memory selector device with VO 2 layer length of sub-100 nm.
Another issue is that the model requires a finite element solution of the transport equation based on a commercial device simulator.Using few assumptions, the transport equations can be simplified under normal operating conditions.Miller et al. [30] reported minority carrier lifetime in a range of 4-15 μs for VO 2 from a photocurrent decay experiment.The long minority carrier lifetime indicates that the electron-hole recombination is a slow process.Moreover, [29] and [30] demonstrated minority carrier diffusion length of a few microns.Since the length of the device under consideration (Mott selector) is very short (20-80 nm) compared to the minority carrier diffusion length (few microns), the diffusion is not the dominant transport mechanism, and we may ignore the diffusion term in Eq. ( 2).We also assume that the current flow is only in the x-direction: Therefore, ignoring the recombination, generation, and diffusion terms, a simplified electrothermal model is obtained (2) For field-assisted transition, the model is based on the Poole-Frenkel phenomenon, which relates carrier density to the applied electric field and other device parameters as below: where N 0 is the reference value of carrier concentration, ω is the activation energy, β is the Poole-Frenkel constant, and E is the applied electric field.In this mechanism, transition takes place when carrier density reaches the Mott criterion.
The proposed model divides the VO 2 layer into 100 segments in the x-direction and three segments in the y-direction, and we prepared a two-dimensional matrix of variables accordingly.At each simulation step, each segment is either in the metallic phase or in the insulating phase, which affects its parameters (including the mobility and resistivity), and using the finite difference method, Eqs. ( 2) to ( 6) are solved to obtain, voltage, current, and temperature at each segment.When the electric field is not close to the critical field, the barrier lowering due to the electric field effect (Poole-Frankel effect) can be neglected, and we only check the critical temperature (T C ) for the transition.However, when the electric field increases, the field-assisted mechanism based on Eq. ( 8) turns "ON," and the transition takes place when carrier density reaches a critical value (Mott criterion): , where H is the effective Bohr radius.At the end of each simulation step, based on the applied electric field and temperature, criteria for both thermal and electrical transition are checked with logical "OR," and after the transition, the cell parameters are updated.Details of the model derivation were published in our recent paper [25].
In our analysis, we considered a uniform VO 2 layer, and each segment is in either the metallic or insulating phase.Therefore, there is not a considerable concentration gradient that leads to the diffusion before or after the transition, although the drift and diffusion are balanced in the equilibrium.Moreover, there is not any carrier concentration gradient within a segment during the transition.This is similar to the operation of a unipolar junction-less field effect transistor (JL-FET) in the accumulation mode.By ignoring the diffusion term, our model does not capture the effect of local diffusion fluctuations between two neighboring segments, if one is in the metallic phase and the other one is in the insulation phase, but this only affects the accuracy of transition time calculation.However, as we will discuss later in the transient analysis part, the extrinsic characteristics of the devices under test (including parasitic resistance and capacitance) are usually the dominant factors affecting the measured transition time results; therefore, the accuracy of the proposed model depends on comparison with I-V characteristics, and we proposed a simple complementary model to quantify the transition time.
The VO 2 layer length (L VO2 ) is a key parameter affecting the switching dynamics.Details of the model were presented in [25].
We calibrated the proposed model with the experimental device [26], and the device parameters and model calibration parameters are listed in Table 2.The reported VO 2 has length of 20 nm, and the transition voltage is about 0.35 V.Under these conditions, the applied electric field is more than 10 5 V/cm, and the dominant switching phenomenon is Poole-Frankel. Figure 3 shows the I-V characteristics of this VO 2 layer obtained by the model compared with the experiment, which indicates excellent agreement.
The VO 2 bulk is in the insulator state at the beginning (V = 0).During forward sweep, IMT switching is observed at 0.35 V.This means that the selector device turns "ON" at this voltage.In the backward path, the switching is observed at 0.19 V.This shows that the model predicts volatile characteristics of the Mott device.The proposed selector device has high current drive capability; therefore, in the series combination of selector and ReRAM, the ReRAM limits the cell current.Figure 3 indicates that the VO 2 layer has bipolar and symmetric I-V characteristics with respect to the applied voltage, which is an important selector feature for both set and reset operations.

Design requirement for crossbar operation
A 1S1R memory cell in crossbar architecture is illustrated in Fig. 4a.Each cell is addressed for read and write operations by applying a voltage between the selected bit line on the top and the word line on the bottom.For selection of the proper cell, the main concern is the status of unselected neighboring cells.To avoid sneak path leakage during read, write, and erase operations, the selector of the unselected cells should be in the insulator or OFF state.Consequently, it is necessary to apply limited voltages to word lines and bit lines of unselected cells.Kim et al. [31] proposed V/2 and V/3 schemes for the correct operation of the crossbar architecture.The V/2 scheme is demonstrated in Fig. 4b.During read or write operation, full voltage (V Apply ) is applied to the selected cell, and the V Apply /2 is delivered to all other unselected word lines and bit lines.Maximum voltage applied to unselected cells that share either the word line or the bit line with the selected cell would be V Apply /2 which is called disturb voltage.Therefore, a significant requirement for correct operation is that the disturb voltage should be lower than the threshold voltage for IMT of the selector to avoid sneak path leakage.Similarly, Fig. 4c illustrates the V/3 scheme in which V Apply and 0 are applied to selected word line and bit line respectively, while V Apply /3 and 2 × V Apply /3 are delivered to unselected word lines and bit lines, respectively.In this scheme, the disturb voltage in the worst case is reduced to V Apply /3.The main requirement is to ensure that the unselected cell's selector is not turned ON by the disturb voltage, even if its ReRAM is in a low-resistance state (LRS), while the selected cell's selector is switched ON, even if its ReRAM is in a high-resistance state (HRS).In general, the V/3 scheme is more flexible and provides a better margin; however, it requires three supply voltages and is more complicated.Another critical design consideration is to limit the maximum current flow of the selected word line to avoid electromigration phenomena.Therefore, the maximum suitable current is limited to 135 μA, assuming a line area of 30 × 30 nm 2 for a Cu metal line.Table 3 summarizes Fig. 4 a A simple crossbar architecture with four 1S1R cells that word and bit lines are used for addressing.b V/2 scheme and c V/3 scheme addressing 1S1R cells to perform read, write, and erase operation the requirements for the correct operation of the 1S1R cell for both V Apply /2 and V Apply /3 schemes.

Results and analysis of 1S1R memory
The simulation results for the 1S1R cell presented in Fig. 4a based on the specifications of the VO 2 selector [26] and ReRAM [18] are shown for "write (set)" and "erase (reset)" operations in Figs. 5 and 6, respectively.Figure 5a shows the I-V characteristics of the selector and the ReRAM elements separately, and Fig. 5b shows the I-V characteristics of the complete 1S1R cell during SET operation.We assumed that the ReRAM is in HRS initially (at V = 0 V).Based on simulation results, the selector turns "ON" at 0.39 V instead of 0.34 V while the "Set" voltage for the ReRAM does not change from 1.63 V; this is because the voltage drop over the selector is obtained from the resistance division between the two components.The memory cell selector turns "OFF" during the backward sweep at 0.125 V, which is called the holding voltage.
Figure 6a shows the I-V characteristics of the selector and the Mott elements separately during "Reset," and Fig. 6b shows the I-V characteristics of the 1S1R cell obtained from simulation.The "Reset" operation is performed when the ReRAM is in LRS.A current jump observed at V = −0.39V during forward sweep is the signature of the selector turning "ON" (IMT).This jump is small because of the selector's high drive capability.The complete erase operation is performed when the voltage reaches −2.5 V. Therefore, a low current level is observed during backward sweep in Fig. 6b.
The design requirements for the integrated 1S1R structure are summarized in Table 4. Design requirements are met for the read operation in both V/2 and V/3 schemes.However, the write and erase requirements are not met.For a correct write operation, the selector should be OFF in the worst case for the applied V write /2 or V write /3.But since V write = 1.63 V, this condition cannot be met by the proposed selector because it turns on at 0.39 V, which leads to the formation of the sneak paths.For erase operation, the situation is even worse because V erase = −2.5 V. Consequently, the proposed structure does not work correctly in a crossbar structure, and a modification is required.

Modified 1S1R cell characteristics
To meet the design requirements for write and erase operations, we propose a modification of the selector cell based on our electrothermal model [25] briefly described in Sect.2.2.The key idea is to increase the threshold for undesirable turn "ON" of the neighboring cell's selectors.To achieve this, we increase the length of the VO 2 layer ( L VO 2 ).This reduces the electric field over the selector for the same applied voltage.Other parameters are kept unchanged to ensure minimum deviation from the reference structure.The length of the VO 2 layer is increased from 20 to 40 nm, 60 nm, and 80 nm.I-V characteristics of the modified selectors are illustrated in Fig. 7.The IMT threshold voltage is increased from 0.34 V to 0.68 V, 1.01 V, and 1.35 V for the samples with L VO 2 (nm) = (40, 60, and 80), respectively.Furthermore, the MIT switching threshold and the width of the hysteresis loop are also increased with the VO 2 layer length.These results provide a degree of freedom to design the 1S1R cell according to the specified requirements.
The "Set" (write) operation and "Reset" (erase) operation of the modified 1S1R cell for the abovementioned selector lengths are illustrated in Fig. 8.For a write operation, the ReRAM element is in the HRS at the beginning, and the applied voltage is increased from 0 to 2 V.The selector turns on at V th-IMT (V) = (0.39, 0.73, 1.06, 1.37) for the cells with L VO2 (nm) = (20, 40, 60, 80), respectively.After selector switching, the cells are almost the same because the conductance of VO 2 layers in the metallic phase is negligible compared to the ReRAM cell, therefore V write = 1.63 V for all cells.In the backward sweep and when the ReRAM is in LRS, the MIT threshold voltages are increased monotonically, V hold (V) = (0.125, 0.30, 0.46, 0.61) for the samples with L VO2 (nm) = (20, 40, 60, 80), respectively, as shown in Fig. 8a.
Figure 8b demonstrates the erase operation when the ReRAM is in LRS.The selector's absolute turn-on threshold voltage is increased from 0.39 V for the original sample with L VO 2 = 20 nm to 0.73 V, 1.06 V, and 1.37 V for the samples with L VO 2 (nm) = (40, 60, and 80), respectively, while the erase voltage remains −2.5 V.The reason is that the voltage drop over the Mott selector in metallic phase is negligible compared to the ReRAM during erase operation.
Table 5 summarizes the design requirements for proper read, write, and erase operation in all modified 1S1R structures.
Given the V write = 1.63 V and V erase = −2.5 V, the selector with 40 nm oxide length does not meet the requirements Fig. 5 Results obtained from simulation of "Set" operation for the VO 2 selector [26] and ReRAM [18].a I-V characteristics the selector and the ReRAM elements separately.b I-V characteristics of the 1S1R cell (the selector with the ReRAM).Red squares represent the forward sweep from 0 to 2.0 V, and blue circles show the backward sweep from 2.0 V to 0. The black triangles represent the forward sweep voltage from 0 to 2 V for a cell in LRS mode (Color figure online) for proper write and erase operations in the V/2 scheme, and the erase condition is not satisfied even in V/3 schemes.The 80 nm selector requires a very large read voltage (V read = 1.4 V), which means that the margin between read and write is very small, and it is not acceptable because of the device-to-device variability and the noise; however, write and erase requirements are met for this device.The best design option for the selector is the device with a 60 nm VO 2 layer.This device meets all the requirements for the V/3 scheme as specified in Table 5.The margin between read Fig. 6 Results obtained from simulation of "Reset" operation for the VO 2 selector [26] and ReRAM [18].a I-V characteristics the selector and the ReRAM elements separately.b I-V characteristics of the 1S1R cell (the selector with the ReRAM).Red squares represent the forward sweep from 0 to −2.5 V, and blue circles show the backward sweep from −2.5 V to 0. The black triangles represent the forward sweep voltage from 0 to −2.5 V for a cell in HRS mode (Color figure online) and write operations is about 0.6 V which is acceptable.The operating voltage range of the read, write, and erase are specified in Table 5.These results demonstrate that the proposed electrothermal model can be used effectively to analyze and improve the memory cell during the design phase.

Transient analysis of the cell access time
The access time of memory cells is an important design parameter.Here we neglect the delay related to the interconnects and only take into account the intrinsic delay for set and reset operations of ReRAM along with the response time for IMT/MIT operations.The turn-on time for the selector determines the read access time, and the write/erase time is the sum of selector turn-on time and ReRAM write/erase time.Consequently, for the transient analysis, the characteristics of ReRAM and selector are studied separately.
Figure 9 shows the simulated transient characteristics for "Set" and "Reset" operations of the ReRAM cell [18].The applied voltage for the "Set"/"Reset" operations is 2 V/−2.5 V respectively.The voltage is applied in the form of a pulse with the rise time of 10 ns, as illustrated in the insets of Fig. 9.The "Set" operation is high-speed (t set = 1.2 ns; we supposed the difference between the time that the applied voltage reached 2 V and the time when the current reached its maximum value as the "Set time").The "Reset" operation requires more time as indicated in Fig. 9b; the time scale for the reset operation is about 6.6 ns (~ 7 ns) (the time difference between application of V applied = −2.5 V and when the current reaches 50% of its final value is considered the "Reset time").Several studies have reported the transient behavior and IMT/MIT switching for the VO 2 structure [32][33][34][35][36][37], showing that transition time in VO 2 depends on the length and cross-section of the active layer [34,35].In addition, in [35], the dependency of the transition time on the voltage amplitude and the input pulse width is discussed.The transient response of the selector is studied based on experimental data because, first, the proposed model only captures the DC characteristics, and second, we would like our analysis to be based on experimental evidence.The 20 nm selector in [26] has a cross-section of 5 × 10 4 nm 2 .A similar structure has been reported in [35], with a length of 100 nm and a cross-section of 3 × 10 4 nm 2 , and the switching time of 800 ps has been reported for IMT and MIT.Another study suggests a transition time of 2 ns in VO 2 with length of 100 nm and 1 × 10 4 nm 2 cross-sectional area [36].Consequently, we expect the IMT and MIT switching time for the selector to be in the range of 1 to 2 ns.A simple RC model is proposed in [33] to approximate the time constant for the transition.After the transition to the metallic phase, the electrical resistance of the selector decreases by several orders, whereas the dielectric constant of VO 2 increases [39].For example, the relative permittivity of VO 2 increases from 36 in the insulator phase to 6 × 10 4 (real part) in the metallic phase at 100 °C [39].This indicates that the time constants for IMT and MIT are in the same order [33].
Based on the above discussion, there are two scenarios to estimate transition time for the selector.In the optimistic scenario, the resistance of the selector in the insulating phase increases proportionally with the length of the VO 2 layer, while the dominant capacitance is considered the lateral capacitance between the selector and surrounding area, which decreases by increasing L VO2 , and the RC model suggests that the time constant remains unchanged; experimental evidence for this scenario is presented in [38].In this case, we keep the IMT switching time in a range of 1 ns for all selectors from 20 to 80 nm VO 2 lengths.In the pessimistic scenario, the dominant capacitance is the intrinsic layer capacitance between the two electrodes and increases with the VO 2 length.Therefore, the RC time constant is proportional to the square of the oxide length ( t RC ∝ L 2 VO 2 ); experimental evidence for this scenario is reported in [39].Taking the switching time of 1 ns for the 20 nm selector, we obtain switching time of 4, 9, and 16 ns for selectors with length of 40, 60, and 80 nm, respectively, based on the pessimistic scenario.
Table 6 represents the range of the access times expected for the read, write, and erase operations based on the abovementioned scenarios.This result is especially interesting for the 1S1R cell with 60 nm selector length, which meets the design requirements for valid operations, and suggests that the read access time is between 1 and 9 ns, write access time is in the range of 2.5 to 10.5 ns, and the erase access time is between 8 and 16 ns, which are practical values for fast NVM.
to analyze and study the design requirements of the 1S1R cell.Simulation results suggest that the model follows the current-voltage characteristics of experimental devices during read, write, and erase operations.We studied the variation of the selector VO 2 length as the design parameter to achieve the design requirements, and simulation results suggest that the selector with the VO 2 layer length of 60 nm can meet all design requirements.We further studied the access time for the memory cell based on experimental results and the first-order RC model, and we obtained the worst-case access time on the order of 9, 10.5, and 16 ns for read, write, and erase operations, respectively.These results Fig. 9 Transient characteristics of the ReRAM device reported in [18].a The "Set" operation with the response time of 1.2 ns (inset shows the applied voltage pulse); b the "Reset" operation with the time constant of 6.6 ns (inset shows the applied voltage) suggest that the proposed IMT model can be used for the design of selector-based NVM cells.

Fig. 1 a
Fig. 1 a Schematic cross-section of the ReRAM element.CF stands for the conductive filament formed in response to an applied voltage in the middle part of the HfO x oxide.b Schematic cross-section of the VO 2 Mott selector element

Fig. 2 I
Fig. 2 I-V characteristics of the ReRAM obtained by the model compared with experimental results.a "Set" or write operation.The red line is the model characteristics in the forward direction (0 to 2.0 V), and the blue line corresponds to model characteristics in the backward sweep.Black triangles represent the experimental data.b "Reset" or erase operation.The red line is the model characteristics in the forward direction (0 to −2.5 V), and the blue line corresponds to model characteristics in the backward sweep.Black triangles represent experimental results (Color figure online)

Fig. 3 I
Fig.3I-V characteristic of the VO 2 layer IMT obtained by the model during forward and reverse sweep and compared with experimental data[26]

Fig. 8 I
Fig. 8 I-V characteristic of the modified 1S1R cells with selector VO 2 lengths of 20, 40, 60, and 80 nm. a The "Set" or write operation; b the "Reset" or erase operation

Table 1
[18] of parameters and constant values used for the ReRAM model calibration[18]

Table 2
[26] of experimental device parameters and model calibration parameters for the VO 2 Mott selector[26]

Table 3
Design requirement and limitation for correct read, write, and erase operation of a 1S1R cell in a crossbar structure based on V/2 and V/3 operating schemes

Table 4
Design requirement analysis for read, write, and erase operations of the 1S1R cell with V/2 and V/3 schemes