Study And Investigation of Silicon Extended Source Vertical Double Gate Tunnel Transistor For Analog/RF Performance

In this paper, a Silicon Double Gate tunnel ﬁeld-effect transistor with Extended Source (ESVDG-TFET) is disclosed while addressing the need for dc/switching and analog/RF applications using Silvaco-Atlas simulator which is used to examine and explore the performance of the proposed device. The mechanics of band-to-band tunnelling and accompanying carrier injection are used to illustrate the operation of the proposed silicon ESVDG-TFET device. The gate is designed to overlap with extended source region along with N+ pockets and channel in order to facilitate both the lateral and vertical tunnelling . The silicon ESVDG-TFET provide lower subthreshold swing of 10.1 mV/decade that allow higher ratio of I ON / I OFF ≃ 10 13 for optimized device structural parameters with threshold voltage of 0.35 V. Moreover, peak transconductance of 800 uS/ um, cutoff frequency of 82 GHz, gain bandwidth product of 16.8 GHz and transit time of 1p sec is obtained by proposed device.


Introduction
Tunnel field-effect transistors (TFETs) have been considered as an alternatives to traditional metal oxide semiconductor FETs because of the beauty of this novel transistor as it deliver steeper switching characteristics (SS is not limted to 60 mV/dec) and has a wide scope for low power SOC design (allow voltage scaling ). The physics of TFET is based on BTBT imparting immunity against various short channel effect. [3] Although the ON-state current of the TFETs is low due to the lack of BTBT (band-to-band tunnelling) probability at the source/channel junction. The probability of tunnelling is proportional to the energy band, charge carrier effective mass, gate oxide thickness and tunnelling barrier width [1] [2]. Many studies have been published in recent years to improve the TFET's performance [6] - [18] Although the majority of researchers has focused on TFETs for low-power switching applications. Many efforts are being made around the world to improve ION, including the use of: 1) a low-bandgap material in the tunneling region [5]; 2) a double-gate architecture [6]; 3)Pocket doped double gate structure [7]; 4) a high-k gate dielectric [6]; 5) hetero gate dielectric [1] [8]. Low subthreshold swing (SS), low threshold voltage (Vt) and a high ON-state current (I ON ) to OFF-state current (I OFF ) ratio are all desirable performance parameters for low-power switching and analog/RF circuits including high transconductance (g m ) and high cutoff frequency( f T ) Various efforts are made by researchers as reported in the literature to enhance the dc and analog/RF performance parameters. Wei Li et al. [9] the author proposed HTG-TFET (Heterojunction TFET with a T-Shaped Gate) having following performance index I on as 7.02A/m and SSavg = 44.64 mV/dec. The author addressed the problem of miller capacitance with the help of Si/SiGe hetero-junction with different doping composition and gate overlap structures. B. S. Reniwal et al. [10] impact of device engineering on DGT-FET with gate underlap and different dielectric spacer material concept used to enhance dc and ac characteristics for SOC application. The author has reported g m as 4.4 uS and f T as 5 GHz and GBP of 1.8 GHz for UL-LKHG DG-TFET. T. Joshi et al. [11] presented a Extended source DG-TFET in which entire source in placed in the channel only by varying S W an improvement in DC/RF parameter is reported. SSavg of 12.24 mV/dec, I ON / I OFF ratio of 2.5 * 10 12 , g m as 238 uS/um, f T of 37.7 GHz and GBP as 3.4 GHz. Jang Hyum et al. [12] reported VS-TFET with vertical channel sandwiched by doped Si facilitating perpendicular tunnelling and gradual doping profile to address I AMB , I ON / I OFF as 10 4 and SSmin of 17 mV/dec.In comparison to the traditional counterpart, X.Zhao et al. [13] informed an L-shaped TFET to improve the BTBT rate and I ON . LDD combined with HGD structure to reduce ambipolarity. Shupang CHen. et al. [14] suggested a silicon T-shape TFET (TG-TFET) with an SS of 24.4 mV/decade and an I ON / I OFF of 6.7 * 10 10 . The TG-TFET has a g m of 232 uS/m and a f T of 11.9 GHz, as investigated by the authors.In various other reported literature, researchers proposed advantage of vertical TFET over planer structure and its fabrication ease [15]. P. Wang et al. [16] improve average SS by suppressing low electric field with epitaxial tunnel layer in TFET structure. Exhaustive use of Si/Ge epitaxial layer in the channel have been reported. [20] In this article, extended p+ source is made to overlap with gate electrode and 2nm silicon epitaxial layer to facilitate both vertical and lateral tunnelling to improve dc and analog/RF performance. The ESVDG-TFET improves I ON and as a result, I ON /I OFF , SS, and V t significantly improve. Furthermore, double gates and scaled device dimensions allow better gate control of drain current, resulting in a higher g m , which improves the device's high-frequency characteristics. 2-D commercially available TCAD tool, Silvaco AT-LAS device simulator is used to examine and explore the performance of the proposed device. The proposed Silicon ESVDG-TFET achieves an I ON /I OFF of 1 × 10 13 with an SS of 10.1 mV/decade, according to simulation results. The device has a peak g m of 800 uS/m, f T of 82 GHz and Gain bandwidth product of 16.8 GHz respectively.

Device structure, Fabrication steps and Simulation
The cross sectional schematic of Silicon ESVDG-TFET is shown in fig Fig. 1 and the parameters associated with proposed device are listed in the Table I as shown. The silicon ESVDG-TFET is a symmetrical typed double gate structure made up of a silicon substrate with a thickness of 10 nm (T Si ). The gate electrode is made to overlap with p+ source 10 20 cm −3 of doping concentration and 2nm silicon epitaxial layer (T epi ) of 10 17 cm −3 doping concentration below gate contact. The n+ pocket and n-channel region is doped with concentration of 10 19 cm −3 and 10 17 cm −3 respectively . T body and L s represent the height and length of the source, respectively. Similarly L c for channel length which is choosen to be 20nm. The doping concentration in the n+ drain region is 10 19 cm −3 . A stacked gate oxide near source region (2-nm SiO2 and 1-nm HfO2) and as one reaches near the 2nm epitaxial layer oxide thickness ( T ox ) of HfO2 reduces to 1nm upto drain end with a gate work function of 4.2 eV. The proposed device has a part of source p+ extended into channel under the gate which is differ from recently reported ESDG TFET in this entire source is grown under channel.
The proposed silicon ESVDG-TFET structure can be fabricated in the same way as reported [19] [23]. In Fig. 2 the proposed ESVDG TFET's fabrication steps are depicted. The source region is defined using a photoresist mask, and then P+ implantation is performed followed by oxidation which is used to grow 2-nm SiO2. After that, rotate the structure at right angle epitaxial growth of 2 nm silicon with doping type and concentration similar to the intrinsic channel is carried out [5]. In similar fashion N+ is implanted to form drain region with defined doping concentration. In the succeeding step, oxidation is done to form gate oxide layer of 1-nm HfO2 then metallization and patterning are carried out to form the front and back gate of the ESVDG-TFET then source and drain contacts.
In order to study various physical phenomena and its effects in a TFET, relevant models are included in the AT-LAS device simulator [27]. To study the recombination phenomenon Shockley-Read-Hall (SRH) with concentration depend life-time model is included. The non-local BTBT tunneling model is taken into account to analyze quantum tun- neling in the device. The traps and dislocations at the interface of epitaxial layer are studied using the non-local trapassisted tunneling model, which is based on the Wentzel Kramer Brillouin (WKB) transmission coefficient [1], [2].
To account for the effect of heavy doping, a band-gap narrowing model and Fermi-Dirac statistics were used. The simulation setup's accuracy is validated in the simulator by implementing a fabricated TFET [28]. We exhibit a comparison of simulated data and measured value transfer properties of a manufactured TFET. The experimental results are substantially identical to the simulated data plot as shown in Fig. 3. 3 Results and Discussion

DC Analysis
Using energy band diagrams, BTBT tunnelling and electric field distribution enhancement in on current can be better described with the help of Transfer characteristics within the framework.In non-local models, the most widely used method to calculate tunnelling probability is the WKB approximation based on charge carrier transmission probability (TWKB) function of tunneling barrier width is formulated as[1] where E g is the bandgap, m * is the effective carrier mass, ε ox , t ox are dielectric constants and oxide thickness. Also, ε Si and t Si are the silicon dielectric constants and body thickness and ∆ φ is the energy range over which tunneling can take place.
In Fig. 4 the device's transfer characteristics is presented for varying Vgs at Vds = 1.0 V, as indicated in plot. When energy band are not aligned at Vgs = 0 V a weak off current flows of order 1 * 10 −16 . The drain current found to be independent of gate voltage in OFF-state. This region is marked by generation and recombination current (temperature dependent) dominates I OFF . In subthreshold region that is near threshold voltage at Vgs = Vth = 0.35 ( corresponding I d = 10 −7 ) as determined by constant current method [1] and reduction in SS. Further increase in Vgs I d is primarily governed by BTBT hence becomes less temperature-sensitive.   Tunnelling enhances at source-channel junction and sourcesi epitaxial layer as it behave as channel for electrons tunneling vertically and then drifted toward the drain under the influence of drain voltage. In order to fully comprehend the working operation the energy band diagrams of proposed device along the cut-line AA' is displayed in Fig. 5. It is clear from figure the source region's valence band is unable to align with conduction band of Si-epitaxial layer when Vgs = 0 V , so the off-state current is very low as device is in OFF-state. Now as the gate to source voltage is increased band bending along band lowering take place and at a certain gate voltage the source region's valence band gets align with conduction band of Si-epitaxial layer. This leads to steep increases in the current. In addition increase in the gate bias leads to reduction in tunneling barrier length and further increase in the current as illustrated in Fig. 6. giving the confirmation of line tunneling.
Further, Fig. 7 and Fig. 8 illustrates the energy band diagram along cut-line CC' at OFF-state ( Vds = 1 V, Vgs = 0 V) and at On-state ( Vds = 1 V, Vgs = 1 V). On increasing the gate potential energy barrier height and tunnelling width λ decreases giving rise to point to point tunnelling. Similarly, Fig. 9 shows the energy band in ON and OFF-state when a lateral cut-line along BB' is made. It is observed a large band gap toward the left most end due to presence of SiO2 oxide layer. A narrow energy band of Si-epitaxial layer and drain region is present owning to silicon material. Increase in gate bias voltage leads to band lowering providing a channel for tunnelled electron. Fig. 10 shows the variation in carrier concentration ( electron and hole ) along the cut-line C-C' as marked in the device near off state( Vgs = 0 V and Vds = 0.1 V ) and in on state ( Vgs = Vds = 1V ). It can be seen that large carrier concentration exist at the source-pocket-channel interface. Fig. 11 is plot of I ON and I OFF with source length.   It is seen that increase in the source length results in more tunnelling area availability, thus increase I ds , however at the same time degradation in off current also follow thus a need for choosing optimum L S is necessary which is 22nm for silicon ESVDG TFET at which max I ON / I OFF is obtained while keeping L G = 20 nm. Fig. 12 illustrate non-local band to band tunnelling for hole and electron for V gs ranging from 0V to 0.5 V for better understanding of proposed Silicon ES-VDG TFET. Fig. 13 shows the electric filed variation along the cutline CC' as marked in the device. As it can be seen the peak electric field exist at the source-pocket-channel interface. It is also worth noting that the peak of the electric field of 5.15 MV/cm at pocket doping concentration of 10 18 cm −3 which is higher than the peak 4.6 MV/cm in the absence of pocket that to say channel doping concentration of 10 17 cm −3 . Lateral tunnelling width λ which decrease with gate bias can be seen in energy band diagram. Fig. 14 depicts electric field variation along the cut-line AA' as marked in the proposed device. The maximum electric field value lies at the interface of source -silicon epitaxial of value 6.5 MV/cm for doping concentration of 10 17 cm −3 which is higher than 6.3 MV/cm for doping concentration of 10 16 cm −3 . The increase in electric field with increase in doping concentration values establish direct dependency of electric field on doping thus helps in increasing the value of current within the channel doping parameter limit of International Technology Roadmap for Semiconductors(ITRS). Further, minimum electric field value of 0.02 MV/cm illustrating that mostly tunnelling take sourcechannel and epitaxial interface and least in the middle of proposed device body and significantly higher drain current flows as a result of line tunnelling. Fig. 15 depicts on current variation for different pocket doping concentration along the cut-line C-C' also schematic of device includes net doping concentration in all the region. It can be inferred as doping concentration increase electric field gets intensified near junction. Hence I ON current increase but this increase in doping must follow International Technology Roadmap for Semiconductors(ITRS) [33]. However in our case pocket doping of 2 * 10 ( 19) is chosen as improvement in current and Sub-threshold-swing is noticed. Fig. 16 From the output characteristics it can be seen that at low Vds channel potential grows as the drain potential rises, resulting in a significant increase in current. Once drain voltage exceed gate voltage channel potential turn to be independent of drain potential thus a good saturation value off drain current (0.325 mA/um at Vgs = Vds = 1.4 V ) for proposed silicon ESVDG TFET and value of 4.5 uA/um at Vgs = Vds = 1.4 V for simulated reference device vertical Si dual material gate TFET. Thus ESVDG TFET outperforms with other two structures.   Fig. 17 is a transconductance variation plot which is pivotal parameter for analog application. The amplification potential of a device is divulge by its transconductance that is more is the elevation, better is the input voltage conversion to current output as formulated in equation It can be seen from above figure improvement in transconductance (△g m ) is in order of two decade between proposed device (silicon) and VSiDMG TFET and VGeDMG TFET shows only 3x improvement with ESVDG TFET.

AC analysis
The suggested device's suitability for RF applications is discussed next. The parasitic capacitance exploration is vital to study ac behaviour at high frequencies. The extraction of capacitance in the simulator is done though small signal analysis at frequency 1MHz. Response at high frequency is mainly governed by gm and total capacitance ( Cgg ). As it can be seen from Fig. 18   f T , GBP and transit time, at high frequency are important parameter of concern. Higher the value of first two parameter of the device more suitable for numerous analog applications. The device cutoff frequency ( f T ) is determined by gm and Cgg which can be formulated as From Fig. 19 it can be observed f T increases with Vgs due to direct dependency on gm but as soon as it attains a peak value of 82GHz near 1V, it begins to decline due to rapid increase in the value of Cgg. However, An improvement of nearly two decade can be seen when compared with silicon ESVDG TFET and simulated reference device VSiDMG TEFT. Similarly it can be observed from Fig. 20 GBP in-creases with Vgs due to direct dependency on gm and inversely on Cgd but as soon as it attains a peak value of 16.8GHz near 1V, it begins to decline due to rapid increase in the value of Cgd. However, An improvement of nearly two order of magnitude can be seen when compared with silicon ESVDG TFET and simulated reference device VSiDMG TEFT. The device GBP which can be formulated as In Fig. 21 the device's transit time is presented for varying Vgs at Vds = 1.0 V, as indicated in plot. In general higher switching speed ( lower transit time) is the desirable characteristics for a device which can be formulated as At lower gate to source voltage τ seems to high due to low value cut-off frequency and decline with increase in Vgs. An overall improvement in silicon ESVDG TFET of nearly two order of magnitude can be observed when compared with simulated reference device VSiDMG TEFT. From Fig. 22 Similar observation in case of TFP parameter exist TFP expressed as (g m * f T )/I d

Conclusion
The Silicon ESVDG-TFET is demonstrated with the source extended into the pocket followed by channel. The structural dimension of silicon ESDG-TFET have been optimised in order to increase line and point tunnelling. Atlas 2-D simulations are used to examine the proposed device's analog/RF performance parameters. The silicon ESVDG-TFET improves metrics like V t , SS, I on / I o f f , g m , f T , and GBP significantly. Double gates structure have superior control over the tunnelling barrier at optimum dimensions, resulting in higher g m , improved f T , GBP, τ and TFP of order of two decade when compared with silicon based other vertical DG-TFET. Hence, Silicon ESVDG-TFET is a better candidate for low power switching and analog/RF performance applications.