Electrostatic characteristics of a high-k stacked gate-all-around heterojunction tunnel field-effect transistor using the superposition principle

We use the superposition method to model the electrostatic characteristics of a high-k stacked gate-all-around heterojunction tunneling field-effect transistor (TFET). The heterojunction is formed from Ge/Si material in the source/channel, respectively. The modeling is accomplished by considering the space-charge regions at the source–channel and drain–channel junctions and in the channel region. The surface potential in the channel region is obtained by applying the superposition principle derived in the source/drain region by solving the two-dimensional (2D) or one-dimensional (1D) Poisson’s equation, respectively. Furthermore, the electric field and the drain current are modeled by using the surface potential and the Kane model, respectively. The results are confirmed using ATLAS technology computer-aided design (TCAD) simulations.


Introduction
Following years of continuous downscaling, transistors based on complementary metal-oxide-semiconductor (CMOS) have suffers from deterioration of the subthreshold swing (SS), the leakage current, and the threshold voltage (VT) [1][2][3]. In addition, the power crisis faced by device engineers led to the emergence of multigate/gate-all-around FETs, group III-V-based FETs, super-steep subthreshold slope FETs, and graphene/carbon-nanotube-based FETs. The tunnel FET is one such device which has attracted attention from researchers because of its low subthreshold swing (< 60 mV/decade) and reduced short-channel effects [4,5]. A three-terminal p-i-n device, where the source and drain are oppositely doped while the channel is either intrinsically or lightly doped, is called a TFET. Such a device has two junctions, namely the drain-channel junction (JDC) and source-channel (JSC). The carrier transport in a TFET is controlled by band-to-band tunneling (BTBT) rather than thermionic emission as in metal-oxide-semiconductor FETs (MOSFETs). Although such devices exhibit low SS and I OFF values, they also suffer from low I ON and ambipolar conduction [6,7]. In this regard, alternative approaches such as gate engineering (i.e., employing multigate/gate-all-around structures) [8][9][10], gate dielectric engineering (i.e., making use of high-k material for the gate dielectric) [11], work function engineering (i.e., employing asymmetric instead of symmetric gate work functions) [12], tunnel engineering (i.e., introducing a heavily doped source pocket at the JSC such that its completely depleted) [13], and materials engineering (i.e., using lower-bandgap materials such as InAs, GaAs, InGaAs, SiGe, or Ge as an alternative to Si) [14] have been proposed to mitigate the shortcomings of TFETs.
Over the decades, various analytical models have been reported for the electrical parameters, in particular the surface potential, electric field, threshold voltage, and drain current, of single/double-gate and GAA TFETs [15][16][17] with single/dual-material gate (SMG/DMG) electrodes. The electrical results for such devices were examined by Verhulst et al. [15]. The 2D electrostatic response of DG and GAA TFETs was reported by Pan et al. [16]. Vishnoi et al. [17] proposed the BTBT current model for DG-GAA-TFETs, irrespective of the depletion regions at the JSC and JDC, by using pseudo-2D analytical modeling. The DMG in a DG-TFET exhibits better drive current and SS than its SMG counterpart according to Kumar et al. [12] and Jain et al. [18]. Kumar et al. [19] and Prabhat et al. [20] reported modeling of the drive current and surface potential of the DMG for SG/DG TFET structures, respectively. The device performance can be enhanced by replacing SiO 2 with pileup SiO 2 and a high-k dielectric in DG TFETs, as reported by Kumar et al. [21]. The proposed Ge-Si-Si hetero stacked gate dielectric GAA-TFET device provides better I ON per unit area than counterpart planar devices. Hence, developing an accurate model for the surface potential, electric field, and drain current becomes important.
The model is validated against previously published reports [31] and three-dimensional (3D) numerical simulations [22]. The remainder of this manuscript is presented as follows: Sect. 2 and 3 discuss the device architecture and results, followed by the conclusions.  Table 1. Three depletion regions are considered in the modeling, namely regions I, II, and III, corresponding to the source-channel, channel, and drain-channel, respectively. The lengths of these regions are considered to be L 1 , L 2 , and L 3 . The potentials across the corresponding regions are 0 , 1 , 2 , and 3 . Figure 3 depicts the band profile of the proposed device. When V GS = 0 V (OFF-state) the interband tunneling is inhibited, so no electrons tunnel through the depletion region at J SC . When V GS = 1 V (ON-state) the energy bandgap reduces and interband tunneling is permitted, which allows electrons to tunnel from the source to the channel. The tunneling rate of electrons is high in hetero-compared with homojunction devices due to the narrow-bandgap materials at the source.

The device structure
The derivation of the model Figure 2 shows a 2D view of the device considered in the modeling. The coordinates of the device are denoted by the z-and r-axes, and the junction potentials are given by 0 , 1 , 2 , and 3 at z = 0 ,

The modeling of the potential in the channel
The distribution of the potential in the gate-all-around device is the same as that in the double-gate device structure. The tubular symmetry of the proposed device means that the surface potential is independent of the angular coordinate. Thus, the 2D Poisson equation in cylindrical coordinates is considered for the modeling, being given in the channel region by where ch (z, r) is the potential across the channel and Si is the permittivity of silicon. The charge density of mobile carriers across the channel is expressed as where i is the intrinsic carrier concentration, U T = KT q is the thermal voltage at 300 K, and V is the nonequilibrium quasi-Fermi level with respect to the Fermi level of the source region, with the boundaries given by [23].
The quasi-Fermi level is almost constant in the radial direction [24]. V DS is approximated by be drain-source voltage along the channel, except at the left end of the channel. At the channel, the electrostatic potential boundary conditions are where C ox is the capacitance of the dielectric per unit area.
where r 0 = t Si 2 , ms1,i is the work function of the gate with respect to the silicon material m , Si ,E gSi , 0s , and 0d are the work function of the gate, the electron affinity of Si, the energy bandgap of Si, and the potentials at the left and right end, respectively.
where 1 (r) is the solution of the 1D Poisson's equation obtained as shown below: The boundary condition at the silicon-dielectric interface is The symmetry of the structure is considered by Using Eqs. (12) and (13), the 1D potential is obtained as The boundary conditions to be satisfied by 2 (z, r) are [23] Assuming 2 ∕U T is small, Eq. (16) reduces to the 2D Laplace equation. This approximation is valid for TFETs [25]. The separation-of-variables method is used to derive 2 (z, r) , yielding the expression where J i (x) is the Bessel function of the first kind of the order i. Using Eq. (20) in Eq. (18) gives the relation for the separation factor λ (which should be a positive value) . Applying the boundary conditions in Eqs. (17) and (18) to Eq. (20) yields the expression for the coefficient in Eq. (20) (a detailed derivation is given in the Appendix).
Based on the device dimensions,S 1 , S 2 , and N are given by The total potential across the channel of the proposed device is obtained by adding the potential terms given by Eqs. (14) and (20).

The modeling of the potential in the depletion region of the source
The depletion region across the source cannot be neglected for higher voltages, so the voltage drop across this region must be considered. The 2D Poisson's equation in region R1 is given by where s (z, r) is the electrostatic potential with respect to the Fermi level in the source region and N A is the doping concentration in the source. The electrostatic potential along the r direction can be approximated by a parabolic equation [26].
The boundary conditions used to obtain the coefficient of the parabolic approximation equation are (23) where C f = 2 C ox is the fringing field effect considered by conformal mapping techniques as in Ref. [27]. Applying the boundary conditions to Eq. (28), we obtain the coefficient as

The general solution of Eq. (35) is
The expression for s must satisfy the following boundary conditions:

The modeling of the potential in the depletion region of the drain
For lower gate voltages, the drain length cannot be neglected. Thus, modeling of the potential in the drain depletion region is carried out, neglecting the radial direction. The 1D Poisson's equation in region R3 is expressed as where D(z) is the electrostatic potential with respect to the Fermi level in the drain region and N D is the doping concentration in the drain region. The fringing field is ignored in this modeling. The boundary conditions are: 1.

2.
On integrating Eq. (41) twice and applying the boundary condition, the following expression is obtained: . The electric field in the lateral direction approaches zero at the right edge of the drain depletion region.
The depletion length at the drain region is obtained from the potential model

The modeling of the drain current
The drain current modeling is carried out using Kane's model. The minimum tunneling path length is considered when calculating the tunneling current. The tunneling path is defined as the path between the conduction-band energy point and the valance-band energy point at the tunneling junction where the interband tunneling mechanism takes place. This length show a discrepancy from the shortest tunneling path ( l short ) to the longest tunneling path ( l long ). In Kane's model, the BTBT generation rate ( G BTBT ) of carriers per unit volume and per unit time is given as [28] where | | E z,r | | is the magnitude of the electric field, expressed as | | E z,r | | = √ E 2 z + E 2 r , is 2 for direct-and 2.5 for indirectbandgap tunneling, A Kane and B Kane are Kane's constants with v a l u e s o f A Kane = 3.5 × 10 21 eV 0.5 ∕cm s V 2 a n d B Kane = 2.25 × 10 7 V∕cm eV 1.5 [28,29].
The drain current is derived by integrating G BTBT over the tunneling volume [30][31][32] Since Eq. (47) represents an exponential function of the electric field, the radial term in G BTBT can be neglected. The lateral electrical field in the channel is obtained from the derivative of Eq. (20), expressed as E avg is the average electric field in the z-direction over the tunneling path and can be expressed as [30] where L T is the tunneling path length. Substituting the average and lateral electric fields into Eq. (49) yields dz dr I BTBT is calculated by integrating Eq. (52) over the exponential terms due to the much faster change of the exponential compared with the polynomial term ( 1 z −1 ): where H(z) is defined as

The modeling of the transconductance
The transconductance is derived from the drain current as

Results and discussion
In this section, the results are plotted for the analytical modeling and validated using the ATLAS TCAD simulation tool. The channel length of the proposed model is 50 nm with a source and drain length of 20 nm. The concentrationdependent, Lombardi, Boltzmann, Shockley-Read-Hall,  Figure 4 shows the surface potential profile along the channel length for a gate-to-source voltage of 0 V and 1 V. It is observed that the electron density across the channel increases with an increase in the gate voltage, especially near the drain region. The extension of the drain/source depletion regions is observed at low/high gate voltages. The surface potential profile of the model is close to the simulation results. Figure 5 shows the surface potential profile along the channel length for different silicon thicknesses of 13 nm, 14 nm, and 15 nm. It is observed from this plot that, the thicker the silicon, the higher the value of the surface potential. When the thickness of the silicon is large, the electron density increases, leading to an increase of the conductivity along the channel, which further increases the value of the surface potential. Figure 6 shows the surface potential profile along the channel for different drain voltages of 0 V and 1 V. The plot shows the variation of the potential across the drain region, while it is constant over the source and channel regions. As the drain voltage is varied, the potential profile changes across the drain region due to an increase in the carrier density. Figure 7 shows a comparison plot of the lateral electric field profile for GAA-HJTFETs with and without high-k material. It is observed that the high-k stacked GAA-HJT-FET exhibits a higher electric field profile than the GAA TFET. The peak across the source and channel region is due to the variation of the potential. The peak is low at the drain to channel region of the high-k GAA-HJTFET compared with the GAA TFET. Figure 8 shows a comparison of the drain current variation versus the gate voltage, revealing that the high-k stacked GAA-HJTFET exhibits a higher drain current than the GAA-HJTFET due to the higher tunneling rate. Figure 9 shows the variation of the drain current versus the gate voltage for different work functions of 4.2 and 4.3 eV. It is observed that the OFF-state current is low while the ON-state current is high, thus the I ON /I OFF ratio is high at 10 15 . Figures 10 and 11 show the drain current variation with the drain voltage for different gate voltages of 0.5 V and 1 V. This plot shows that, the higher the gate-to-source voltage, the higher the drain current. Figure 12 shows the variation of the transconductance with the gate voltage. The transconductance is high for the high-k stacked GAA-HJTFET, which in turn increases the sensitivity of the device operation.

Conclusions
Analytical modeling of a high-k stacked GAA-HJTFET is presented. First the electrostatic potential modeling of the high-k GAA-HJTFET is considered. To enhance the  performance and reliability of such devices, the charge carriers across the depletion regions and channel were taken into account. The analysis is accomplished by considering three depletion regions for the channel, source, and drain. The analytical modeling in the channel is carried out using the superposition technique, considering the 1D and 2D Poisson equations. The modeling in the source region is derived using the 2D Poisson's equation with parabolic approximation. The drain region is modeled using the 1D Poisson's equation. The potential distribution modeling is used to obtain the lateral electric field, the minimum tunneling length, and the current of the proposed model. The drain current is modeled using Kane's model, in which the drain current is derived by integrating the BTBT generation rate. The plotted results confirm an excellent match with the simulation results. It is suggested that the model is appropriate for low-power very largescale integration (VLSI) applications. (61)