18nm n-channel and p-channel Dopingless Asymmetrical Junctionless DG-MOSFET: Low Power CMOS Based Digital and Memory Applications

In this paper, an 18nm dopingless asymmetrical junctionless (AJ) double gate (DG) MOSFET has been designed for suppressed short channel effects (SCEs) for low power applications. A desired ON and OFF state current ratio with subthreshold performance parameters under limit, is the major focus of the proposed transistor. Different sensitivity parameters of dopingless AJ DG MOSFET such as drain extension, length of gate overlapping and oxide thickness are compared with the AJ DG MOSFET with doped channel region. The ON-state current obtained is 3.80 x 10−6\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$${10}^{-6 }$$\end{document}A/µm with reduced OFF-state leakage current up to1.37 x 10−17\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$${10}^{-17 }$$\end{document}A/µm. The subthreshold slope (SS) and drain induced barrier lowering (DIBL) of the device obtained are 59.5 mV/decade and 10.5 mV/V respectively. Temperature analysis of proposed device at various temperature such as 250 K,300 K, 350 and 400 K shows a small variation in OFF-state current (< 15 %). Additionally, a p-channel AJ DG MOSFET along with n-channel AJ DG MOSFET are designed and their performance is evaluated for CMOS inverter circuit and 6T SRAM cell. All design and analysis have been done with a 2D/3D Visual TCAD device simulator.


Introduction
The size of the semiconductor devices is being continuously reduced and has entered into the nanoscale range [1]. Every two years the number of transistors doubles because the size of the MOSFET is reduced. oxide semiconductor field effective transistor (MOSFET) is a semiconductor device used in various applications like for analog and RF applications to handle the radio frequency signals that are high in power from devices like television, radio transmitter, amplifiers [2]. For reduction in cost and to increase the speed of the device double gate MOSFETs are taken into consideration [3]. MOSFET's are used for biomedical applications that are used as a biosensor to detect biomolecules like enzymes, nucleotide, protein, and antibodies [4,5]. Application of MOSFET as a biosensor has benefited over other methods as it has more sensitivity, compatibility, mass production and miniaturization [5]. MOSFET is also used for memory applications to store data. 6T SRAM cell using MOSFET was designed to store data that occupies less area in the chip [6]. MOSFETs were also adopted by NASA to detect interplanetary magnetic fields and interplanetary plasma. Low power MOSFETs are desired in digital applications as a switch that prevents DC from flowing through gate thus, reducing power consumption and providing large input impedance. Reducing the size of the MOSFET reduces the size of the channel length which causes short channel effect and it increases the leakage current [7,8]. The reduction in the size of semiconductor devices has given rise to short channel effects (SCEs) [9]. The various short channel effects arise due to parasitic capacitances, drain induced barrier lowering, mobility degradation, hot carrier effects etc. To overcome these effects the devices, need to be engineered using different techniques like gate engineering and channel engineering [2] [ [10][11][12][13][14]. Gate engineering includes changing the material of the gate with different work functions, designing double gate, triple gate and multi-gate structures. Channel engineering includes changing the shape and size of the channel, drain and source regions. The cause of the SCEs is when the width of the drain barrier extends into the drain and source region barrier lowering.
Many MOSFET's structures such as double-gate MOSFET, gate all around MOSFET, triple gate MOSFET, SOI MOSFET, double step buried oxide has been designed to overcome SCEs. Sarkar et al. [14] proposed a Double gate MOSFET having three different gate metals with different work function for enhancement of RF and analog performances. Nasri et al. [15] proposed a tri-gate SOI MOSFET for analyzing the thermal performance of the device and reducing the thermal field in Tri-gate SOI MOSFET. Pakaree et al. [16] designed a class AB amplifier using Double Gate MOSFET for audio amplification and noise reduction. Abhinav et al. [17] design a junctionless Double Gate MOSFET for studying misalignment effects and thermal stability by varying the temperature from 200 to 500 K. Misalignment of the gate causes low performance of the device and reduces ON state current. Srivastava et al. [18] proposed a cylindrical surrounding Double Gate MOSFET. The MOSFET designed is used as A RF switch for the application in wireless telecommunication and is capable of storing more energy than the conventional device. Orouji et al. [19] proposed a SOI MOSFET with double step buried oxide having the advantages of bulk structure as well as SOI structure. This device reduces the self-heating effects with degrade the device performance. Ajay etal. [20] proposed a junctionless Double gate MOSFET with an underlapped gate at the source and drain in two different structures for binding molecules. This structure is used as biosensor in biomedical applications for detecting various diseases. Ajay et al. [21] designed a device junctionless Double gate MOSFET using dielectric modulation technique for detecting biomolecules. Wanget al. [22] proposed a Double Gate MOSFET with asymmetric gates on both sides for improving the performance of the device and reducing the short channel effects (SCEs). Ramesh et al. [23] proposed a Generic Double-Gate MOSFET for better threshold voltage, subthreshold swing, DIBL etc. Andreas et al. [24] designed a threshold voltage model for an undoped symmetrical double-gate MOSFET. This model has been simulated by varying silicon thickness and gate oxide thickness.
In this paper an 18nm dopingless asymmetrical junctionless double gate (AJ DG) MOSFET has been proposed. The structure and dimensions of the device are discussed. Double-gate MOSFET has gate placed in an unsymmetrical manner with different doping in the drain, source and channel. Hf O 2 is used as a gate oxide material. Gate contact material used is p + polysilicon. Drain, source and channel regions are contained in thin silicon wafer. The sensitivity analysis of the proposed device is carried out by varying parameters like drain extension, length of gate overlapping and oxide thickness. The proposed device dopingless AJ DG MOSFET and different doping concentrations in the channel, drain and source region has lowered the DIBL ratio, near to ideal subthreshold slope and increased the I ON =I OFF ratio. The proposed transistor performance has been evaluated at different temperatures ranging from 250 to 400 K. This paper is mainly divided into three sections. Section 1 describes the introduction of different types of MOSFETs and their applications in various field. Section 2 contains detail description of proposed device along with its dimensions. Section 3 contains four different parts. The first part describes the ON and OFF state current of the device. Second part contains the sensitivity analysis of the device and third part is based on the reduction in short channel effects. The Section 4 includes design of an inverter circuit with proposed n-channel and pchannel AJ DG MOSFET for low power and low voltage CMOS based digital and memory applications.

Device Structure and Dimensions
The presented section deals with the design of asymmetric gate junctionless MOSFET for low power and steep subthreshold performance characteristics.

Proposed Dopingless Asymmetrical Junctionless Double Gate MOSFET of 18 nm Channel Length
The proposed structure has two gates asymmetrical to each other as shown in Fig. 1. The proposed dopingless asymmetric junctionless double-gate MOSFET has gate placed in an unsymmetrical manner with different doping concentrations of drain, source and gate. ON and OFF state of the MOSFET determines the length of the channel. When the MOSFET is in ON state the channel length is equal to the overlap region of the gate and when the MOSFET is in OFF state the channel length is equal to the total channel length of the gate minus the overlap region. The total channel length of MOSFET is 18 nm. During ON state the channel length becomes 4 nm (length of the overlap region) and during OFF state the channel length becomes 14 nm (total channel length of MOSFET minus overlap region). The region dimensions and doping levels are specified in Table 1. The source region is highly doped while the drain region is lightly doped and the channel is undoped. The high values of the I ON (ON-state current) with supressed I OFF (OFF-current) are proved to be a suitable choice for low power and high-speed applications.
This design is implemented using Visual TCAD which is based on drift diffusion model. Drift diffusion model depends on the values of electric field, lattice temperature and doping. For semiconductors the value of electric field E and doping concentation of holes and electrons are taken into consideration. The drift diffusion assumption is given by the Eq However the size of the semiconductor has been reduced over the years, therefore the assumptions of Eq. 2.1 is insufficient. Figure 2(a) shows the graph of the electric potential of dopingless AJ DG MOSFET. Electric potential is the potential difference between the surface of the polysilicon gate and the bulk of the MOSFET. When the gate voltage is low the potential of the channel region decreases, with an increase in the gate voltage the height of the barrier reduces (i.e. force of electric field that forms the barrier reduces) and channel potential increases, therefore increasing the drain current. Figure 2(b) represents the electric field of dopingless AJ DG MOSFET. At low gate voltage, there is a sudden increase in the electric field in the channel region that suppresses the leakage current in the OFF-state. The spike in the electric field reduces with an increase in the voltage bias. When positive gate voltage i.e.V gs >0 is applied, electron concentration increases near the interface of oxide and semiconductor and the barrier reduce increasing the flow of electrons from source to drain region during the ON state. During OFF state the barrier increases reducing the leakage current.

ON State Current and OFF State Current of the Proposed Device
The analysis of proposed dopingless asymmetrical junctionless double gate MOSFET with 18 nm channel length has been done by using drift diffusion model in visual TCAD device simulator. The majority charge carrier is n channel MOSFET is electrons. The doping concentration is different for drain, source and channel. Gate voltage and drain voltage increases by if the concentration of electron density is   increased with the corresponding decrease in the concentration of holes. The doping concentration of source is increased to 1x10 19 cm À3 equal to that of the channel region and the doping concentration of drain is reduced to 1x10 15 cm À3 .The channel region is undoped that is made of thin silicon wafer.
The drain region has lower doping concentration to minimize the hot electron effect. Due to the scaling of MOSFET the electric field at the drain becomes very high that dislodges the holes. Therefore, to reduces such effects the drain has lower doping concentration. The undoped channel has advantages of having a higher carrier mobility and suppresses the threshold voltage variation caused by random dopant fluctuation. Source, Drain and channel region is made of thin silicon wafer of 6 nm thickness. Dopingless AJ DG MOSFET has simpler structure when compared to self-aligned FinFET which more complex to design. Also, FinFET have shown more complex fabrication steps than DG gate Planner MOSFET. The result obtained by dopingless AJ DG MOSFET is shown in Fig. 3. In this, ON-state current is increased and there is a reduction in OFF-state current therefore increasing the I ON =I OFF ratio and improving the performance of the device. It is observed that the introduction pocket region in the channel significantly suppresses the short channel effects (SCEs).  The oxide thickness taken is 1nm, 3nm, 5nm. When oxide thickness decreases, the gate has better control over the channel region. It can be seen from the graph that dopingless AJ DG MOSFET has uniform variation in the graph and the OFF-state current keeps on reducing with a decrease in oxide thickness. Doped AJ DG MOSFET with equal doping has a kink in the graph at a lower voltage and is not uniform as compared to dopingless AJ DGMOSFET. The kink in doped AJ DG MOSFET is formed due to surface trap at the gate. As the oxide thickness increases the surface trap density increases and gate control reduces causing the formation of the kink. Therefore, dopingless AJ DG MOSFET shows better performance and is less sensitive to change in thickness of the gate oxide. Figure 5(a) and (b) shows the sensitivity of dopingless AJ DG MOSFET and AJ DG MOSFET with equal doping by changing the length of the drain (Lext). The length considered is 8nm, 10nm, and 15nm. It is observed that dopingless AJ   [22], hence dopingless AJ DG MOSFET region is more robust and less sensitive to change in the length of extension of drain as there is no variation in OFF state current. Figure 6(a) and (b) show the variation of the overlapping region in dopingless AJ DG MOSFET and AJ DG MOSFET with equal doping. The length of overlapping considered is 6nm, 10nm and 16 nm. It is observed that dopingless AJ DG MOSFET shows negligible variation in the graph compared to AJ DG MOSFET with equal doping. For fixed gate length the variation in overlap region has very less effect on subthreshold performance which is favourable in case of any misalignment. Such a dopingless AJ DG MOSFET can be compared with self-aligned FinFET in terms of low self-alignment issues arises due to fabrication defects. Hence, dopingless AJ DG MOSFET can be a suitable choice for high performance and low power applications.

Reduction in Short Channel Effects (SCEs)
Drain induced barrier lowering (DIBL) is a short channel effect in which the threshold voltage reduces with increases in drain voltage. The DIBL ratio is calculated using δV gs =δV ds mathematically. The DIBL ratio obtained is 10.5 mV/V at gate length 20nm.Subthreshold slope (SS= dV gs dðlogI dÞ ) is a short channel effect which occurs in the subthreshold region when there is leakage in the current. The slope of the drain current and gate voltage during the subthreshold region gives SS. This parameter reduces the performance of the device. The proposed structure suppresses the SS to 59.5 mV/decade than the other structures as shown in Table 3. Figure 7 shows the comparison of the DIBL value and SS value for dopingless AJ DG MOSFET and Doped AJ DG MOSFET. The DIBL and SS value for dopingless AJ DG MOSFET are less compared  The dopingless AJ DG MOSFET has been also used as biosensing application with the help of additional biosensing cavity regions with different geometry and sizes [28,29]. Since, these devices are at nano level in size, so it can be implanted anywhere as per required.

Temperature Analysis
Temperature analysis describe the device stability towards temperature variations. Lesser is the variation in drain current, lesser will be the variation power consumption which is desirable for digital and memory application.    Figure 8 shows the temperature analysis of dopingless AJ DG MOSFET. The temperature is varied from 250 to 400 K with step size of 50 K. The increase in temperature increases the OFF state current and there is no significant change in the ON state current. OFF state current of the device at 250 K is 2:36 Â 10 À19 , 300 K is 3:50 Â 10 À17 , 350 K is 1:64 Â 10 À15 and 400 K is 5:56 Â 10 À14 .Therefore the ratio of ON state to OFF state current reduces thereby degrading the performance of the device. As the temperature increases, the OFF state current or the leakage current increases due to two reasons (1) current due to thermal generation (2) current due to impact ionization (process in which electron hole pairs are formed in huge amount that leaks through the depletion region generating current. Figure 9 represents the p-channel dopingless AJ DG MOSFET asymmetric has gate placed in an unsymmetrical manner with different doping concentrations of drain, source and gate which gate contact as n + polysilicon. Gate oxide ( HfO 2 ) has thickness 1 nm. Source and drain region has p type doping with concentration of 1x10 19 cm À3 and 1x10 15 cm À3 respectively. Channel region is undoped. Length of the channel region is 18 nm. Length of overlapping region L overlap is 4 nm. Length of the drain and source regions is 8 nm. Figure 10 shows that matching of nmos and pmos. Also, pmos and nmos are compatible with each other with similar threshold voltage and drain current variations. Therefore, both the nmos and pmos can be used for designing of CMOS inverter [30]. Figure 11 represents inverter design using n-channel and pchannel of dopingless AJ DG MOSFET (proposed NMOS and PMOS). The input of the device is given through the gate   contact of both NMOS and PMOS. The ratio of the width of PMOS and NMOS is taken as 2:1. All the four gates are interconnected to each other. Output of the device is received through the drain 1 and drain 2 interconnected to each other. When the input given to NMOS is smaller than the threshold voltage of NMOS then NMOS of the inverter remains in cut off region. The PMOS in this case is in linear region and drain current of NMOS and PMOS is zero. Therefore, the output voltage becomes equal to the supply voltage. When input voltage is greater than threshold voltage of PMOS + supply voltage, then PMOS works in cut off region and NMOS in linear region and the drain current is zero therefore the output obtained is zero as NMOS is connected to the ground. Both the drains are interconnected to each other. Source 1 is connected to VDD and source 2 is connected to GND. In Fig. 12, when the input is 1 the output received is 0. The inverter inputoutput variations indicate an ideal behaviour showing perfect logic 0 and 1. This shows that the proposed dopingless AJ DG MOSFET is compatible with CMOS technology and useful for low power digital circuit and memory design such as SRAM and DRAM cell. Leakage current is major design constraint for low power applications. So, dual material gate can be additional choice for gate engineering to do further reduction in leakage current [31]. The device can further explore for analog/RF performance by designing an amplifier with proposed n-channel and p-channel MOSFET [32].

Fabrication Steps of Inverter
Fabrication of CMOS inverter is designed using NMOS and PMOS integrated over the same silicon wafer as shown in Fig. 13. Fabrication includes the steps to create silicon wafer, oxidation, exposure to UV rays through specific glass mask based on mask layout and creating active window for n-MOSFET and p-MOSFET followed by metallisation.
Silicon wafer of doping concentration of 1x10 16 cm À3 is taken as the as the substrate that is thinned down to 6 nm. Gate oxide HfO 2 of 1 nm is grown on both sides of the wafer for NMOS and PMOS. Ion implantation is used to add impurities to drain and source region. This method accelerates the dopants to 20-100 keV and the depth of penetration can be decided by increasing or decreasing the accelerating voltage of the ions. Polysilicon gate is layer is deposited over the oxide region using the chemical vapour deposition process. Polysilicon gate is deposited using silane or trichlorosilane. Pure silane or solution of silane with 70-80 % nitrogen is used to ensure the growth of the layer with temperature range between 600 and 650 0 C with pressure of 25 and 150 Pa.  Figure 14 represents 6T SRAM cell [33] that is designed using dopingless AJ DG MOSFET. It has nodes WI, BI, Blb, these nodes are connected to the probe for studying the voltage level on the probe. The probe is based on inverters that are cross connected. The drain of the PMOS of the first inverter is connected to the drain of the NMOS of the first inverter and the drain of the PMOS of the second inverter is connected to the drain of the NMOS of the second inverter. The source of both the PMOS of the inverter is connected to Vdd, and source of both the NMOS of the inverter is connected to ground. The gate of NMOS and PMOS of first inverter is connected together and to the node connecting the drain of PMOS and NMOS of the second inverter. The gate of the NMOS and PMOS of the second inverter are connected together and to the node connecting the drain of NMOS and PMOS of first inverter. Figure 15 presents the hold state of 6-T SRAM cell using proposed complementary MOS transistors. In hold operation the SRAM cell is in static state and stores the data. When the Word line is 0 V the transistor n3 and n4 are in OFF state and from the figure it can be seen that 0 and 1 value is retained in the inverter. Figure 14 describes read operation of 6-T SRAM cell with proposed NMOS and PMOS transistors. During the read operation both the bit lines BL and BLB are pre-charged. When the word line is raised to 1.8 V, the node that is storing 0 pulls down one of the bit lines whereas the other bit line remains pre-charged. The data stored is read through the voltage that is present at the bit line. Therefore, from the graph it can be seen that the voltage in the bit line BL and BLB has the same data as that of V out and V out when the word line (WL) is V DD . Figure 16 describes the Write operation of 6T SRAM cell. Write operation can be performed using either one of the transistors n3 or n4 which is connected to V DD or GND. To write 1 to V out1 both the bit lines BL and BLB is charged to V DD . The word line is asserted to V DD to enable the transistor n3 and n4. From the figure it can be observed that when the values of BL and BLB is forced to 1 or 0 the output of inverter 1 and inverter2 is changed accordingly.

Conclusions
The proposed 18nm dopingless AJ DG MOSFET has gate placed in an unsymmetrical manner with different doping concentration in the drain, source and channel. The short channel effects (SCEs) which arise due to scaling of MOSFET is suppressed more in Dopingless AJ DG MOSFET, therefore improving the performance of the device. The I ON =I OFF ratio increases (~2.77 × 10 11 ), the ideal value of subthreshold slope (59.5 mV/V) and DIBL (10.5 mV/V) value is lowered. Analysis of Sensitivity between dopingless AJ DG MOSFET and AJ DG MOSFET with equal doping has been compared and observations are made. Different sensitivity parameters of dopingless AJ DG MOSFET such as drain extension, length of gate overlapping and oxide thickness are varied for both the device structures. It is observed that dopingless AJ DG MOSFET is less sensitive to change in the parameters and the device is more robust than doped AJ DG MOSFET. The proposed structure dopingless AJ DG MOSFET is less sensitive and provides better subthreshold performance. Different temperatures such as 250 K, 300 K, 350 and 400 K were considered for temperature analysis of the device. With increasing temperature, the leakage current increases due to increase in thermal current and impact ionization current which increases the OFF state current and reduces I ON /I OFF current ratio. This shows the device suitability for low power digital and CMOS based large capacity memory applications. Pchannel dopingless AJ DG MOSFET is designed. Matching of nmos and pmos of AJ DG MOSFET is shown in the paper. A complimentary dopingless AJ DG MOSFET (n-channel and p-channel) issued to design a lower power inverter circuit and 6T SRAM cell with ideal voltage characteristics.