Performance Evaluation of Epitaxial Layer Based Gate Modulated TFET (GM-TFET)

This paper reports the performance of an epitaxial layer (ETL) based gate modulated (GM-TFET) through 3D Technology Computer Aided Design (TCAD) simulations. The architecture utilizes effects of both vertical tunneling and lateral tunneling phenomena to improve the device performance. Attributes of the ETL, its thickness (tepi) and doping concentration (Nepi) are varied and their impact on device electrical parameters such as transfer characteristic, output performance, subthreshold swing (SS), and threshold voltage (VT) is highlighted. It is observed that both tepi and Nepi significantly influence the different electrical parameters of the ETL based TFET architecture.


Introduction
Over the year, extensive research is carried out to control the various restrictions of short channel effects (SCEs) of MOSFET [1]. In this aspect, novel devices with different operation mechanism is proposed in the literature. Tunnel Field Effect Transistor (TFET) which operates on band to band tunneling (BTBT) mechanism instead of thermionic emission and it has subthreshold swing (SS) below 60 mV/dec. at 300 K [2,3]. One of the foremost disadvantage of TFET is its low ON state current [4,5]. Various research have been presented through structural engineering to enhanced the ON current of TFET like silicon on insulator (SOI) TFET [6], heterojunction TFET (HJ-TFET) [7], circular gate TFET (CG-TFET) [8], double gate (DG) TFET [9], dual material gate (DMG) TFET [10] and many more. Also, epitaxial layer (ETL) based TFET architecture is proposed to make TFET suitable for low power applications [11,12]. The gate overlapped on the source and drain regions is one popular approach to enhance the performance of TFETs with high tunneling at ON state [13]. Furthermore, source pocket doped with line tunneling TFET has been highlighted to improve the conduction of TFET [14]. The ETL based TFET provide the vertical tunneling along with lateral tunneling, which improves the tunneling probability and enhanced the ON current [15]. Such ETL based TFET is a potential candidate to boost the performance of TFET. A gate modulated (GM)-TFET having ETL with improved ON current for the variation in gate and drain bias is reported [16]. The source/drain lateral straggle (σ) influence on analog and high frequency performance of GM-TFET is investigated in literature [17]. Also, the linearity performance of GM-TFET for the variation of σ parameter is highlighted [18]. It is highlighted that the RF/analog performance are improved, whereas, short channel behavior are degraded as the lateral straggle parameter increases in Ge source dual material double gate (DMDG) TFET [19]. In our recent work, we have reported the linearity performance for the variation in lateral straggle parameter in Ge source DMDG-TFET and linearity behavior degrades as the lateral straggle parameter is increased [20]. An investigation on RF/analog and linearity parameters considering interface trap charge in dual material gate oxide stack double gate (DMGOSDG) TFET is highlighted and reported that this device is more immune to trap charge compared to conventional DMG-TFET [21]. A triple heterojunction TFET with 12 nm body thickness has SS value of 40 mV/dec. with ON current 325 µA/µm is reported by Chen et al. [22]. However, the performance of GM-TFET is not evaluated for various ETL thickness and doping concentration of the ETL.
In this work, the effect of ETL thickness (t epi ) on transfer characteristic, output characteristic, SS and threshold voltage (V T ) of GM-TFET is reported at fixed value of doping concentration of the ETL (N epi ) through Technology Computer Aided Design (TCAD) device simulator. We also highlighted the effect of N epi on these electrical parameters of GM-TFET at fixed value of t epi .
The organization of the paper is as follows: Section 2 describes the device architecture along with simulation methodology. Section 3 provides the simulation results obtained from simulator and the same is discussed here. This work is summarized in Section 4.

Device Structure and Simulation Descriptions
The 2D representation of the GM-TFET with ETL is shown in Fig. 1(a). The epitaxial layer of the ETL GM-TFET is placed over the source and channel portions i.e. under the gate dielectric layer. In conventional TFET structure only lateral tunneling is present at tunnel junction perpendicular to gate field. In ETL GM-TFET, the vertical tunneling along with lateral tunneling improves the conduction mechanism of TFET [14]. The BTBT rate of the proposed structure obtained from the simulator is shown in Fig. 1(b). Here, source, drain, channel as well as the epitaxial layer (ETL) is made of Silicon. SiO 2 having dielectric constant of 3.9 is taken as buried oxide, whereas, HfO 2 having dielectric constant of 22 is considered as gate dielectric. Metal having work function (ɸ M ) = 4.02 eV is taken as gate material. The uniform doping concentration is considered for all regions. The p + source doping concentration of (N S ) = 10 20 cm -3 is considered as greater than n + drain doping concentration (N D ) = 5 × 10 18 cm -3 to minimize the ambipolar current [23]. The intrinsic channel has doping concentration (N ch ) = 10 15 cm -3 , whereas, doping of epitaxial layer (N epi ) is varied, otherwise mentioned. The various dimensions of the parameters as shown in Fig. 1(a) are listed in Table 1.
Sentaurus TCAD tool is used for the simulation of the device [24]. Masetti mobility model is considered to study impact of doping concentration on charge carriers and Fermi Dirac distribution is enabled due to presence of degenerate source/ drain regions. As tunneling probability is dependent on energy bandgap and thus bandgap narrowing model is adopted. The recombination of the carriers is considered by enabling SRH model in simulator. The transport of the carriers in simulator is activated by considering non-local BTBT Kane's model in simulator, which captures BTBT at the required junction. The experimentally calibrated fitting parameters of BTBT is chosen in simulator are: A path = 1.63 × 10 14 cm -3 s -1 , B path = 1.47 × 10 7 V cm -1 , P path1 = 0.0567 eV [25].  Length of source region (L S1 ) 7 5 Length of intrinsic region (L int ) 2 5 Length of drain region (L D ) 3 0 Length of gate region (L G ) 1 0 0 Silicon layer thickness (t Si ) 2 0 Height of BOX (t box ) 1 4 5 Height of bulk (t bulk ) 1 0 Oxide thickness (t ox ) 3 Epitaxial layer thickness (t epi ) varies

Results and Discussion
This section described the influence of epitaxial layer thickness (t epi ) and doping concentration of ETL (N epi ) on transfer characteristic, output characteristic, SS, and V T of ETL based GM-TFET through device simulator. The drain to source bias (V DS ) = 0.5 V is taken. The threshold voltage reading is taken from simulator through maximum transconductance method that is the gate voltage where transconductance is maximum.

Influence of Epitaxial Layer Thickness (t epi )
Here, the analysis is presented for t epi = 4, 6, 8, and 10 nm at fixed N epi = 10 15 cm − 3 .
The effect of t epi on transfer characteristic by varying t epi from 4 to 10 nm with step of 2 nm, while keeping all other dimensions fixed, in linear and log scale are presented in Fig. 2(a) and (b), respectively. It is seen that ON current increases significantly, whereas, OFF current degrades insignificantly, with the decrease in t epi . This improvement in ON current can be better explained from Fig. 3, where we have plotted eBTBT rate at source-channel junction for V G =1.5 V and V DS = 0.5 V, taking t epi as parameter. It is perceived from Fig. 3 that the BTBT rate increases for lower value of t epi which signifies improvement in ON current of the device as summarized in Fig. 2(a).
The effect of t epi on output characteristic for V G = 0.5 V, of ETL based GM-TFET is portrayed in Fig. 4. It is perceived (Fig. 3) that eBTBT rate rises with reduction in t epi , which indicates carrier can easily flow from source to drain as t epi changed from 10 to 4 nm. Thus, the drain current saturation occurs at large V DS for high value of t epi , whereas, for low value of t epi saturation occurs at low value V DS .
The I ON , I OFF , and I ON /I OFF ratio as a function of t epi of GM-TFET is summarized in Table 2. It is seen that as t epi  increases the I ON degrades, whereas, I OFF is improved by an observable amount. However, the switching ratio (I ON /I OFF ) is enhanced as t epi is changed from 4 to 10 nm. The variation in SS and V T taking t epi as parameter is shown in Fig. 5. As the subthreshold characteristic improves with rise in t epi , which leads to improvement in switching performance and accordingly, SS value decreases. The reduction in t epi increases ON current, which in turn reduces the threshold voltage to turn on the device and the threshold voltage changed by 1.46 % as t epi is increased from 4 to 10 nm.

Influence of Epitaxial Layer Doping Concentration (N epi )
This section discussed the electrical parameters by changing N epi from 10 15 to10 18 cm -3 while keeping other design parameter constant at fixed t epi = 8 nm.
The influence of N epi on input characteristic in linear and log scale are presented in Fig. 6(a) and (b), respectively. It is seen that with increased N epi , there is improvement in ON current as well as minute degradation in OFF current. As concentration of epitaxial layer increases, which enhanced the BTBT rate at tunnel junction and accordingly, improves the ON current.
The I ON , I OFF , and I ON /I OFF ratio for the variation in N epi of GM-TFET is shown in Table 3. As the value of N epi is increased, the I ON is increased, whereas, the I OFF degrades and this leads to degradation in I ON /I OFF ratio.
The output performance as a function of N epi is portrayed in Fig. 7. It can be summarized that electrons can travel fast from source to drain regions with increased in N epi , which indicates the drain current saturates at large drain bias as N epi is changed from 10 15 to 10 18 cm -3 .
SS of MOSFET can be expressed as [26]: SS ¼ ln 10 10 @V GS =@ ln n m ð Þ ð Þ ð 1Þ The minimum concentration is expressed as  The inversion charge carriers Q inv of MOSFET is given by [27].
where, n i is the intrinsic concentration, q is the electronic charge, ɸ S,min is the minimum potential, and φ t is the thermal voltage. This Q inv is related charge is directly related with the threshold voltage.
The influence of N epi on both SS and V T is summarized in Fig. 8. As OFF current of ETL based GM-TFET increases with rise in N epi , which degrade the corresponding SS value. It is examined also from (1) and (2), the SS is inversely related with N epi , which leads to degradation in SS value with increased N epi .
Also, less V T is needed to make the device on with increased N epi and this is primarily due to enhanced ON current with rise in N epi . It is also observed from (3) that Q inv reduces with the increased in N epi and this decreases the required gate bias to activate the channel. The changes in threshold voltage of 1.27 % is found as N epi is changed from 10 15 to 10 18 cm − 3 .

Conclusions
We have elaborated the performance of ETL based GM-TFET for the variation of ETL thickness (t epi ) and doping concentration of ETL (N epi ). Simulation results reported that the increased in t epi degrades the ON current and improves SS of GM-TFET. The roll-off in threshold voltage (V T ) is observed when t epi decreases from 10 to 4 nm. Furthermore, the increase in N epi , enhanced the ON current, whereas, degrade the SS of GM-TFET. It is also analyzed that upto N epi = 10 17 cm -3 the roll-off of V T is lesser and when N epi increases to 10 18 cm -3 the V T falls by significant amount. The output current improves for low (high) values of t epi (N epi ) in GM-TFET. Therefore, lower value of t epi with heavily doped ETL (N epi ) can boost the performance of GM-TFET.
The less roll-off in threshold voltage along with improved I ON /I OFF ratio in GM-TFET is observed for N epi = 10 18 cm − 3 . On the other hand, SS value of less than 60 mV/dec. and better I ON /I OFF ratio is achieved at t epi = 10 nm. Therefore, N epi = 10 18 cm − 3 and t epi = 10 nm are considered as optimized values with improved electrical characteristic in GM-TFET.  Fig. 7 Effect of N epi on output characteristic Disclosure of Potential Conflicts of Interest The authors declare that he has no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.
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