Simulation-Based Analysis of Ultra Thin-Body Double Gate Ferroelectric TFET for an Enhanced Electric Performance

The ultra thin body double gate FE layer TFET (UTB-DG-FE-TFET) is proposed and investigated in this work. Electrical performance parameters such as surface potential ψ (x), electrical field, drain current, sub-threshold swing, threshold voltage, and Ion/Ioff ratio are further analyzed using simulation-based analysis. Integration of Si: HFO2 ferroelectric layer on top and bottom surfaces make the structure that provides negative capacitance, higher on current, enormous surface potential, peak electric field, and improvement in SS with degradation in off Current. The suggested design is evaluated in comparison with FE-TFET and standard TFET structures. Finally, the impact of device geometry variants like ferroelectric layer thickness (tfe), intrinsic channel thickness tsi, interfacial layer types, interfacial layer thickness (tox) and channel length Lc on transfer characteristics are investigated through 2D TCAD Sentaurus Simulator for a clear validation of its optimization. The recommended work demonstrates that it is a suitable device enabling superior performance and helpful in ultra-low-power applications.


Introduction
Short channel effects (SCEs) and an increase in leakage current are the main issues with downscaling the CMOS technology node [1][2][3][4]. Moreover, at room temperature T=300K, the scalability of threshold voltage V T is also limited due to Boltzmann tyranny (SS ≡ KT q . ln 10 ≈ 60 mV/decade) that decides the steepest nature of the transition between on and off state [5][6][7][8][9]. In short, there is a need for in-depth research on steep subthreshold swing devices (< 60 mV/decade) like Tunnel field-effect transistors (TFETs) [10,11], Impact ionization MOSFETs (I-MOS-FETs) [12], Nano-electro-mechanical FETs (NEMFETs) [13] and Negative capacitance FETs [14]. These Emerging devices have been seriously explored in recent years due to impending physical constraints of conventional CMOS devices. Thereby TFETs or commonly called the green transistors, Girdhar Gopal 2019rec9550@mnit.ac.in 1 Electronics and Communication Engineering Department, Malaviya National Institute of Technology Jaipur, Jaipur, Rajasthan 302017, India are the most promising contenders that operate on the quantum mechanical band-to-band tunneling (B2BT) principle [15][16][17]. A most claiming obstacle for TFET being low ondrive-current (I on ) because of less transmission probability T WKB of the interband tunneling barrier [18]. T WKB is estimated using Wentzel-Kramer-Brillouin (WKB) approximation. WKB approximation defines it as exponential function of effective mass m * , energy band gap E g , tunneling length λ, and the difference in energy between both the source's conduction band and the channel's valence band δφ. That is tunneling barrier approximation is estimated by . I on is obtained by integration of T WKB over depth of source-channel junction. Moreover, at fixed drain voltage, a rise in gate voltage V g changes the surface potential, minimizing λ and raising δφ. Thereby, maximum transmission probability T WKB of tunneling barrier implies a greater on-current I on . Accordingly, there are many possible causes to increase I on : (i) The usage of high-K gate material, for example, is a type of gate dielectric engineering technology, service of multi-gate structures for controlling channel potential perfectly, selection of the optimum value of spacer to enhance on-current I on , asymmetric gate design by the use of different work functions and different gate dielectric materials, and ferroelectric gate oxide [19] (ii) Tunneling junction engineerings such as by use of the optimum value of source doping, by increasing effective tunneling area and heterojunction structure by use of low-bandgap materials [11] (iii) Material engineering techniques by use of unique materials like Ge and III-V semiconductors [20] (iv) by use of strained-silicon [21]. However, the ferroelectric gate oxide technique is the best example of negative capacitance that can provide high I on and sub-60 mV/decade at a modest voltage value [22]. Integration of FE layer on TFET has drawn much attention in boosting the performance, i.e., possible structures for negative capacitance TFETs are metal-ferroelectric-insulator-semiconductor (MFIS), metal-ferro-electric -metal-insulator-semiconductor (MFMIS), metal-ferro-electric-semiconductor (MFS) and metal-ferroelectric-insulator-semiconductor-insulator-ferroelectric-metal (MFISIFM) [23]. It is well known that a combination of FE layers in the gate will provide internal voltage gain, which ultimately enhances tunneling probability T WKB and improves on-current [24]. Thus on-current is obtained by integrating tunneling probability T WKB over the source-channel junction. Salahuddin et al. [5] have shown that replacing the standard oxide film with ferroelectric oxide boosts the drive current and lowers the subthreshold swing (SS) in CMOS devices. M. H. Lee et al. [24] found that employing a lead zirconate titanate (PZT) ferroelectric in a stacked gate method may lead to nearly doubling of subthreshold slope (SS) with a 16% increment in drain current. Livio Lattanzio et al. [25] in the initial stages of the research of such kind suggested new structure of TFETs that he named as ferroelectric Tunnel FET (Fe-TFET), with an SS of about 880 mV/dec, based on poly (vinylidene fluoride-trifluoro ethylene) P (VDF-TrFE). Avinash Lahgere [26] et al. suggested a new negative capacitance ferroelectric (FE-TFET) depending on the charge plasma method for improved ON-current and steep SS less than 42 mV/decade. They reported remarkable tenfold progress in on-current, a hundred fold reduction in I off , and I on /I off ratio of 10 11 . Ashish Kumar Singh et al. [27] presented a ferroelectric-based heterojunction TFET on SELBOX with a back gate having a reduced SS value of 38.6 mV/dec and a 9.22 × 10 10 on to off current ratio. Puja Ghosh et al. [28] recently noted an improved-ON current in the range of 10 −5 A/μm and an on to off current ratio of 5.8 × 10 11 with a minimal subthreshold swing (SS) of 29 mV/dec. Although many studies have been conducted to analyze the impact of electrical parameters such as SS, Memory Window, I on /I off ratio, and others for various structural improvements. A prominent structure that exceeds previous efforts is still needed. The proposed negative capacitance structure is MFISIFM, i.e., Ultra-thin body double gate FE layer TFET (UTB-DG-FE-TFET).
In addition, device is also able to be implemented for low powered circuit (e.g., inverter, ring oscillator [1,10] and non-volatile memory like SRAM, DRAM [18,29] etc.). The paper's organization follows with theory in part 2, followed by device construction and simulation setup in part 3, following with results and discussion in part 4. Lastly, part 5 concludes the paper.

Theory
The main reason for using the interfacial layer SiO 2 in between Si : HFO 2 and intrinsic silicon channel in UTB-DG-FE-TFET is to rectify the lattice mismatch problem [14,16,30]. Moreover, Si : HFO 2 is the most compatible with the flow of the CMOS manufacturing process due to its low value of dielectric constant and smoother interface behavior [29]. The enticing characteristic of FE material is negative capacitance, which behaves like a voltage step-up transformer. Therefore, SS and drain current are improved. Any CMOS device's subthreshold swing is generally calculated as the ratio of variation of gate bias potential (V g) to variation of subthreshold drain current by unity decade. Mathematically it can be expressed as: Where m is the body factor used to calculate the effective twisting of surface potential at a specific bias, and n is the transport factor that tells how much current flows along the channel by lowering the potential. From Fig. 1, it is evident that the capacitor voltage divider rule clearly shows that V g and ψ s are correlated, that is where 1 C eq = 1 C ox + 1 C f e is equivalent gate inter-facial capacitance, C ox is inter-facial layer capacitance, C s is semiconductor or intrinsic channel capacitance and C f e is ferroelectric layer negative capacitance. If Q is total charge observed by total capacitance across gate C g then equivalent gate inter-facial capacitance C eq is calculated by following expression: is seen across C eq and voltage in proportional with total charge Q also observed by C g being expressed by ( β.Q) where β is internal amplification factor having value greater than unity. Therefore, 1 then equivalent gate-inter-facial capacitance C eq attain negative value; hence it is called negative capacitance TFET. In other sense, the feedback 1) must be positive to behave as negative capacitance TFET. It also implies amplifying internal voltage and reducing body factor m as clear from Eq. 2. Overall, SS is significantly decreased, as evident from Eq. 1. Moreover, Eq. 1 suggests that ψ s V g , i.e., acts as a step-voltage transformer which ultimately results in an improved electric field and enhanced on-current. In case of MOSFET, body factor m = 1 results into a lower limit of SS= 60mV/decade i.e., Eq. 1 results into SS ≡ ∂ψ s ∂(log 10 I d ) = KT q . ln 10 ≈ 60 mV/decade. Moreover, ferroelectric polarization results in getting body factor m < 1 in the proposed device structure. The benefits of using FE material on the top and bottom surface of the intrinsic channel over perovskite material like PZT and SBT is the best scaling in the nanometer range. Voltage across the MOS (V MOS ) and voltage across the FE material (V F E ) is related by V g = V MOS + V F E . Voltage amplification is given by [31] : With |C f e | is less than |C MOS |, voltage amplification factor yields into negative voltage gain.

Device Construction and Simulation Set Up
The cross-section perspective of the UTB-DG-FE-TFET is depicted in Fig. 1, including its capacitive modeling. The channel is enclosed by an interfacial layer (SiO 2 ) to reduce inter-diffusion. In a stacking having dielectric (SiO 2 ) on sidewalls, a ferroelectric sheet of silicon doped hafnium oxide (Si:HFO 2 ) is utilized.
Because of the lower value of the dielectric constant (32.5), Si:HFO 2 is preferred over Strontium Bismuth Tantalate (SBT) and Lead Zirconate Titanate (PZT) to lessen the impacts of fringing [32,33]. It enables thinner ferroelectric layers. As a result, the gate stack ratio is better for scaling. Furthermore, Si:HFO 2 is compatible with the CMOS manufacturing process flow [17]. Design must always utilize an interfacial layer with the substrate to minimize lattice mismatch and enhance SS. However, the memory window is restricted owing to a voltage drop throughout the interfacial layer [34]. As a result, the best value of t ox = 0.5 nm is chosen. The source is highly doped, via an impurity concentration of 10 20 cm −3 , compared to a weakly doped drain with an impurity concentration of 5 × 10 18 cm −3 , to diminish ambipolar conduction. The channel is weakly doped, while not being entirely intrinsic, with a trivalent impurity concentration of 10 16 cm −3 . Table 1 lists the device variables used in the simulation. On the 2D TCAD Sentaurus Simulator, the device construction is simulated and tested [35]. Applying Fermi-Dirac statistics and the impact of band-gap narrowing, heavy doping at the drain, and source concerning channel is studied. Concentration-dependent mobility model, electric field-dependent mobility, band-gap narrowing model, Schockley-Read-Hall (SRH) recombination model, auger recombination model, and non-local band to band tunneling (BTBT) model are some of the models that are employed throughout computations. Ideal ferroelectric sheet having remanent polarisation P r , coercive field E c , and saturation polarisation P s are 10.75 μ C/cm 2 , 1.15 MV/Cm, and 11.37 μ C/cm 2 , respectively, to eliminate hysteresis loss difficulties such as dc breakdown, retention, as well as fatigue [36]. For gate material, the proper work function (ψ m = 4.6eV) is used.

Simulation Results and Discussion
The effect of ferroelectric thickness on electric parameters in UTB-DG-FE-TFET is discussed. The paper investigates and conventional TFET [37,38]. Simulated data of UTB-DG-FE-TFET is compared with reference data of FE-TFET and conventional TFET, which shows proposed UTB-DG-FE-TFET, which indicates the high value of on current I on and significant change in off current I off . In addition, it must be noted that because of the negative capacitance and the double gate construction, the drain current level rises. The drain current I ds rises as the gate voltage V gs increases. Memory window is key deciding parameter for description of total dipoles and can be expressed as MW ≡ 2E c × t fe , here E c as well as t fe denote coercive field or coercivity and ferroelectric material thickness, respectively [29]. Comparison of the electrical characteristics of the proposed work with previously published simulation results of such devices is listed in Table 2. The suggested device has an SS of 23 mV/dec and an I on /I off ratio of 7.11×10 13 .
Increasing the channel length to 30 nm, a large area of tunneling junction may be achieved in the suggested TFETs that lead to increment in the ON current.

Comparison of TCAD Model Physics with Referenced Data
Transfer characteristics of UTB-DG-FE-TFET are examined and simulated using experimental parameters shown in Table 1 and also compared with FE-TFET [30] and conventional TFET [37], respectively in Fig. 2. Proposed UTB-DG-FE-TFET almost provides two times improvement in I on and 20 times improvement in I on in comparison with FE-TFET and conventional TFET, respectively. One can observe that the proposed structure also gives 10 1 times reduction in I off and 10 2 times reduction in I off as compared to FE-TFET and conventional TFET, respectively. Internal voltage amplification, such as that provided by a voltage step-up transformer, is the cause of this occurrence, which finally yields into increment in I on and reduction in I off , i.e., it leads to enhancement in the current level. Due to the particular hysteresis behavior of FE materials, forward and reverse sweeps for voltage are introduced in transfer characteristics for the proposed structure in Fig. 3. Comparison of output characteristics of UTB-DG-FE-TFET with FE-TFET and conventional TFET at V gs = 1 V is illustrated in Fig. 4. In triode region up to V ds = 0.2 V, a channel is formed due to the availability of large charge carriers, and when the V ds is increased beyond 0.2 V, the large numbers of charge carries starts to tunnel. Thus, I ds shows a growing exponential curve due to the lowering of drain induced barrier. The lateral electrical field from the drain is halted through the channel. That's why a perfect saturation is also seen in output characteristics [39].
Moreover, incomplete charge compensation and decrease in polarization also happened due to depolarization field in FE materials. Figure 5 illustrates that approximately the same window is granted for two different structures of 15 nm gate length UTB-DG-FE-TFET and 30 nm gate length FE-TFET by sweeping the gate voltage. Comparison results  Apart from data storage properties of FE materials, the surface potential of UTB-DG-FE-TFET is boosted over FE-TFET, and conventional TFET, and the output current level is amplified [24]. For this purpose, the change in the channel surface potential of UTB-DG-FE-TFET, FE-TFET, and conventional TFET to the varied value of V gs is presented in Fig. 6. Additionally, Fig. 6 depicts the change   Table 1 is depicted by symbols in the surface potential curve as a measure of channel length from source to drain for UTB-DG-FE-TFET as determined by TCAD simulations. The entire length of the channel is assumed to be 30 nm. Every 10 nm, potential changes are detected. When the channel length grows up to 10nm, it is apparent that the surface potential of UTB-DG-FE-TFET grows exponentially. As the length of the channel advances from 10 nm to 20 nm, the surface potential response climbs gradually, and it takes a little jump and then grows as the length of the channel rises. This implies that short channel effects (SCEs) are minimized, and on the drain side, the gate material behaves like a screened gate. The sudden shift primarily in potential profile caused by the extensive work function of metal seen in Fig. 6 is attributable to higher carrier velocity and therefore improved carrier transport efficiency, leading to a rise in the drain I ds . According to Fig. 6, the UTB-DG-FE-TFET has no significant difference in potential from FE-TFET and conventional TFET on the source side but a negligible difference on the drain side. Finally, as before shown in Fig. 4, V ds has a minimal impact on I ds after saturation, and irrespective of the supplied drain bias voltage, there is a minimal change within the proportion of the lowest surface potential. In general, as the gate voltage rises, so does the height of the barrier on the source and drain sides. Thereby, the surface potential increases in the channel area. During the V gs sweep, the surface potential of the UTB-DG-FE-TFET was amplified above that of the FE-TFET and conventional TFET, which increased the B2BT. Figure 7 demonstrates the comparison of UTB-DG-FE-TFET electrical fields with FE-TFET and conventional TFET [32]. Under the bias conditions having V gs = 1 V and V ds = 0.5 V, the maximum electric field for UTB-DG-FE-TFET at the interface of source and channel is 37.5% greater than conventional TFET and 10% greater than FE-TFET. This is owing to the excellent characteristics of positive feedback caused by FE materials.

Effect of Ferrothickness on Subthreshold Swing, Threshold Voltage, Electric Field Dependent Polarization and I on/I off
Due to negative capacitance, voltage is amplified to a great extent but with negative potential gain. Subthreshold swing is a crucial parameter for understanding any MOS switching behavior [4]. It is found that Polarization of ferroelectric layer improves the value of point subthreshold swing SS point as shown in Fig. 8. Figure 8 shows that as t fe varies from 4 to 16 nm, SS point value is reported below 36 mV/decade for a range of approximately ten orders of magnitude. Average sub-threshold swing SS average is noticed around below 45 mV/decade in Fig. 9 for the various value of t f e . Because the subthreshold properties are significantly improved, the device is appropriate for ultra-low energy switching applications. Figure 10 demonstrates the relation between threshold voltage V th and intrinsic channel thickness t si for different values of t fe . The figure also reveals that as the intrinsic channel thickness tsi and the FE layer thickness t fe increases, so does V th . This was primarily because the tunneling volume was reduced with a rise in t si and the feedback charge lowered since t f e increased [32,37]. A FE layer of t fe = 16 nm shows a relatively thinner hysteresis curve having greater polarization on the application of the highest electric field to get deep saturation that is evident from Fig. 11. Therefore, current level enhances in thinner FE layer with maximum negative capacitance. Due to spontaneous polarization in ferroelectric, a nonlinear relationship exists between polarization and electric field, represented by a hysteresis loop. On increasing t fe , magnetic polarization tries to become zero, as illustrated in Fig. 11. Thereby, Coercive field strength reduces inconsiderably. Therefore, simulation results validate that characteristics governing parameter are t fe and memory window value is raised dramatically. The primary concern in the design of the proposed device is to choose an optimum value of FE layer thickness so that three key parameters SS, memory window, and drain current, are improved. Therefore, former is reduced, and the latter is increased. Recently explored silicon doped hafnium oxide (Si:HFO 2 ) is selected not only to provide relatively coercive field E c over PZT (Lead-Zirconate-Titanate) and SBT (Strontium-Barium-Titanate) but also to present a large memory window [29]. Figure 12 depicts a summary of the effect of the ferroelectric device layer thickness on the I on /I off ratio of the ferroelectric device. Figure 12 illustrates that the drive current I on rises as the thickness of the ferroelectric layer decreases due to polarisation trapped charges while the OFF current remains similar. This improves the ratio of I on /I off , as the ferroelectric layer's thickness decreases.
At t fe = 2 nm, it was discovered that the proposed device had a better SS, a large ratio of I on /I off , and a significant   Figure 13 illustrates the logarithmic effect of ferroelectric layer thickness on drain current while changing gate voltage on a linear scale. Table 3 shows the ferroelectric characteristics for different Si:HFO 2 layer thicknesses. Table 4 displays the device's parameter value concerning different device geometry variations. Table 4 demonstrates  that improved SS, large memory window and high on-off current ratio are regarded to be the most suitable value when compared with other variations at t fe = 2 nm, t ox = 0.5 nm, t si = 10 nm, SiO 2 as interfacial layer type and L c = 30 nm . The ferroelectric layer thickness has a significant effect on device performance. Negative capacitance rises as t fe decreases resulting in increased trapped charge density. These trapped charge densities within this ferroelectric sheet create a channel and start a tunneling process at low V gs. It can be shown that when the thickness of ferroelectric oxide t fe increases from 2 nm to 4 nm, 6 nm, etc., the drain current significantly reduces. With an increase in t fe , this results in the creation of a low feedback charge. However, in the absence of the FE layer (t fe = 0), the drain current is observed to be less because of the absence of positive feedback. For t fe > 0, a high current is seen due to positive feedback introduced by negative capacitance. Yet the coercive field E c hardly reduces on increasing t fe . So it leads to an apparent dependency of t fe on the memory window (MW). For this reason, MW rises from 0.21 V to 0.32 V substantially. Figure 14 illustrates the influence of varying the intrinsic channel thickness t si on the I ds -V gs curve. The drain current I ds decreases with t si , as shown in the figure. The reason for this is that when t si rises, the tunneling volume decreases. Moreover, one can notice that the memory window (MW) falls with t si due to a reduction in the coercive field E c . Figure 15 shows the impact of various interfacial layer types, i.e., 0.5 nm SiO 2 layer is replaced by HFO 2 and then by Si 3 N 4 . Detailed analysis is done by SiO 2 only because of two limitations of HFO 2 : (i) lattice mismatch problem between HFO 2 and silicon substrate during fabrication process (ii) deterioration of I on /I off , instead of large ON current and large memory window of 0.56 V.

Effect of Device Geometry Variants on Transfer Characteristics
Impact of various interfacial layer thickness t ox of SiO 2 interfacial layer on transfer curve I ds -V gs is depicted in Fig. 16. For the moderate value of t ox = 0.5 nm, the enormous electric field is induced by a more significant voltage drop in the substrate material at the tunneling interface. Thus, on current increases with greater memory window as compared to a thicker layer of t ox = 1 nm. Effective oxide thickness t ox = 0.5 nm is one of optimum  Fig. 17. It is noticed from the figure that I on remains the same for channel length up to 30 nm while the same I off is obtained for channel length greater than 20 nm. The figure shows that on-current I on decreases for channel length greater than 30 nm, and off-current I off rises for channel length smaller than 20 nm. The best suitable channel length L c = 30 nm is chosen because of the larger I on and memory window.

Conclusions
UTB-DG-FE-TFET is demonstrated using Sentaurus TCAD simulation to investigate electrical characteristics like a surface potential ψ (x), drain current I ds , threshold voltage V th , and subthreshold swing (SS) over conventional TFET and FE-TFET using Sentaurus TCAD 2D simulator. The results indicate that the current level is raised by increasing the gate voltage, with a drop in the off-current compared to other TFETs. It is also noticed that surface potential is boosted along with the channel position, and Fig. 15 The effect of various interfacial layer types on transfer characteristics Fig. 16 The effect of various interfacial layer thicknesses upon transfer curve at the source-channel interface, there seems to be a maximum electrical field. In contrast, V th rises with increment in t si and t fe and thinnest hysteresis loop is obtained for larger t f e . It is also noticed that SS point and SS average are improved against I ds for different value of t fe . Moreover, Effect of larger t fe and t si results into reduced tunneling current. While the type of interfacial layer, especially SiO 2 layer having t ox = 0.5 nm over HFO 2 and Si 3 N 4 is found to be best suitable because of lattice mismatch problem faced by HFO 2 against silicon substrate. In addition, larger on-current as well as huge width of memory window is noted for t ox = 0.5 nm. Finally, channel length L c also has a significant effect on transfer characteristics. Furthermore, a high I on and a very little I off was shown for the proposed design to produce outstanding I on /I off (≈ 10 13 ). Thus, Such TFETs may be appealing for ultra-low-power circuit