Junctionless FETs On Silicon-On-Insulator With Buried Metal Fin For Multi Threshold Operation

In this paper, an n-channel junctionless FET (JLFET) based on SOI with a buried metal n (BMF) is presented. We show that the BMF of suitable workfunction of the proposed device BMF-SOI-JLFET can control the channel electrostatic eld by employing Schottky junction effectively. The enhanced association of potential between BMF and the channel combined with gate electric eld makes it worthy for multi-threshold and dynamic threshold (DT) operation. Additionally, the biasing of BMF projects the broad range of threshold voltage (V TH ) regulation with a high value of body factor (γ). The proposed device demonstrates γ enhancement compared to n body (FB)-JLFET and conventional SOI-JL FET under identical conditions due to constant potential coupling. The DT mode of operation shows a 73% improvement in ON-state current in addition to reduced subthreshold swing contrast to BMF-SOI-JLFET without DT. This paper imparts a viable option for low power applications with multi-threshold operation and high switching speed applications with DT operation.


Introduction
In recent years, the need for devices having increased switching speed and improved device density leads the device scaling to nanometer regime. But, the aggressively scaled devices are more prone to short channel effects (SCEs) -the critical challenges in nanometer-scaled devices. By employing fully depleted silicon-on-insulator (SOI), multigate architectures such as FinFETs with enhanced electrostatic controlling of gate and different conduction mechanism mainly band-to-band-tunnelling (BTBT), we can alleviate the SCEs substantially [1]- [5]. Recently, a junctionless transistor (JLT), which has the same type of dopant impurity in channel and drain/source regions, has been proposed as an apt alternative for nanometerscaled devices. The JLTs present simpler fabrication process, reduced SCEs compared to conventional MOSFETs and lower thermal budget [6]- [8].
The JLTs based on SOI has degraded subthreshold behavior and device performance towards SCEs compared to JLTs built on bulk substrate, as their device performances have been compared in [9], [10].
Moreover, to turn off the SOI JLT devices properly and to have reduced leakage current, either a narrow channel width or high gate workfunction required and it is restricted by the process complexity.
Additionally, bulk FinFETs offer greater exibility by speci ed device parameter for enhanced subthreshold characteristics. In these JLTs, controlling of subthreshold leakage in Si device layer is done by either p-n junction depletion in vertical direction as in BPJLT [9] or by employing a high-κ BOX dielectric integrated with highly doped (p+) substrate [11]. A vertical non-uniform doping pro le (Gaussian) has been used for achieving the same as reported by Mondal et. al. [12]- [14]. Recently, a buried-metal-SOIlateral JLT (BM-SOI-LJLT) has been demonstrated in which buried metal induces bottom depletion by employing Schottky junction, with enhanced ON-to-OFF current ratio [15].
The multigate structures with back-gate/substrate biasing has been reported in various literature [16]- [20], and these devices are operated for multi-V TH with legitimate γ by employing substrate/back-gate bias. This back-gate/substrate biasing offers a way to achieve high performance in ON-state (active mode) and low power in OFF-state (standby mode), it also provides greater exibility in circuit design [21].
Additionally, DT mode of operation has been demonstrated besides of multi threshold operation to enhance the ON-current without expense of OFF state current [22]. In DT mode of operation, varying voltage of electrically connected gate and body terminals changes the body potential dynamically. It has been illustrated that device having high value of γ decreases threshold voltage and subthreshold swing (S.S) drastically which results in rapid increase of ON-state current [23].
The controlling of V TH in FinFET is still aided by substrate bias, however, the enhanced gate controllability in multigate structure negates the channel to substrate coupling which results in smaller γ and it further reduces notably with increase in n height. Recently, Kumar et.al [24] demonstrated that JLFET with n body (FB-JLFET) can attain a large γ owing to stronger coupling between channel and n body (p-n junction coupling). In this work, we propose a SOI-JLFET with a buried metal n underneath the active layer (BMF-SOI-JLFET). Here, we use the buried metal layer concept in FinFET structures instead of planar SOI-JLFET for multi-threshold and dynamic threshold operation. BMF-SOI-JLFET utilizes Schottky junction at bottom interface of channel to obtain a large body factor and, to enhance the electrical performance of it by implementing workfunction variation of BMF, biasing of BMF and DT operation.
The paper is organized in subsequent section. Section II outline the structural detail, conceptual process ow and simulation setup. In Section III, the effect of BMF workfunction and biasing of BMF are analyzed in continuation with DT operation. Lastly conclusions are made in Section IV on the basis of results.

Device Structure And Simulation Setup
The 3-D view of proposed BMF-SOI-JLFET is depicted in Fig. 1, having a thin active layer doped by n-type impurity with channel thickness T CH wrapped on a buried metal n. A stack of gate dielectric with equivalent oxide thickness (EOT) = 1 nm has been used, also gate metal with workfunction 5 eV is employed. Here, BMF-SOI-JLFET utilizes a buried metal (with workfunction φ BM > φ Si ) n of width (W MF) and height (H MF ), which is sandwiched between active n + layer and buried oxide (BOX) of thickness T BOX = 20 nm. It is worth to mention that electrostatic in uence of BMF-SOI-JLFET channel is controlled by top contacts of multigate with added coupling at bottoms of channel by Schottky junction (between active layer and buried metal n). Figure 2 shows the proposed process ow of BMF-SOI-JLFET. Figure 2(a) depicts the initial handle wafer and subsequently oxide is deposited in Fig. 2 (b). After that metal (Co, φ BM = 5.0 eV [25]) can be sputtered using ion-beam sputtering on the patterned seed wafer [26]. (d) The plasma-assisted bonding method is used to bond seed wafer and handle wafer and in subsequent annealing [27], [28]. Fin is patterned after splitting the wafer. In Fig. 2(e), gate oxidation, gate metal deposition and patterning are carried out, after that nitride spacer and contacts are developed in Fig. 2 The numerical simulations are carried out using Sentaurus TCAD simulator [29] in a 3-D work-framework. Simulator solves the Poisson and carrier continuity equations in self-consistent manner to estimate the electrical characteristics of devices. We have employed Drift-diffusion carrier transport model in general.
Fermi statistics model is applied for highly doped Si channel ≥ 10 19 , as the density of state of the conduction band may be lesser than doping levels. Bandgap Narrowing (doping dependent) model is used for highly doped Si channel. Shockley-Read-Hall (SRH) generation and recombination model, and robust Nonlocal BTBT model based on Wentzel-Kramers-Brillouin (WKB) tunneling probability have been included to evaluate subthreshold characteristics. The mobility model-Lombardi model for interface degradation, doping dependent, velocity saturation, are included in our simulation for reliable ON-state current. The calibration of simulation models was accomplished by replicating BM-SOI-LJLT with the same set of device parameters, as shown in Fig. 3(d). Here m e and m h are effective tunneling masses of electrons and holes.

Result And Discussion
In this section, the characteristics of buried metal n-body and its effect on device performance have been discussed, as the workfunction dependent Schottky-induced depletion of channel signi cantly affects the device working. Additionally, the impact of biasing of BMF has been explored for multithreshold and dynamic threshold operation.
A. Impact of Buried Metal Body function difference of gate metal-channel, respectively. As, the effective channel appears thinner than the physical one due to the Schottky induced depletion at the bottom, which would add to gate electrostatic control.
It is noticed that reduced off-state current, lower subthreshold slop [see in Fig. 3(b)], and enhanced ON to OFF current ratio can be achieved by increasing the buried metal ns workfunction. This is because increased depletion in bottom owing to Schottky-induced junction results in a thinner effective channel and enhanced gate electrostatic control. It is also observed that with increasing WF of BMF, leakage current through it also reduces. The reduced OFF state current with increasing workfunction of buried metal can be explained by band diagram and carrier distributions at V GS =0 V and V DS =1V. Moreover, the threshold voltage in JL transistors signi cantly affected by variations in channel dimension and doping [30], [31], the evaluation of Vth variability against T CH for different doping concentration is depicted in Fig 7(b). For xed BM workfunction (5.1 eV), V TH is slightly more sensitive with increased channel doping as observed by Fig 7(b). Furthermore, for xed channel doping, sensitivity of V TH could be enhanced by increased workfunction of buried metal.

B. Impact of Buried Metal Bias V BM
In addition, to explore the impact of buried metal bias on the electrical performance of the proposed BMF-SOI-JLFET the I D -V G characteristics have been plotted for a different V BM as depicted in Fig. 7. On applying of negative voltage on the BM body with speci ed gate voltage, the channel depletes additionally from bottom of the channel interface by elevating energy bands as depicted in Fig 8(a). It could be substantiated by the observing the Figs. 5 and 6, even as, a slight shift of conduction band at junction interface results in change of carrier concentration as well as subthreshold current at given gate voltage. So, V TH is affected by change in V BM as can be observed from Fig. 7.
The standard technique to study the impact of body bias on the I D -V G -characteristics is body factor (γ) parameter. γ is determined by proportion of change in V TH against change in V BM , i.e., γ = ΔV TH /ΔV BM [21] and we extracted V TH by constant current method at 10 -7 A. The demand of high ON-current in active mode of operation and low OFF-current in standby mode for multiple V TH application is achieved by a high valued body factor (γ) transistor. It is noticed that from Fig. 8(a), the gap between conduction band and fermi level is affected by V BM at given gate voltage and hence deviation in V TH . From Fig. 8(b), which shows the estimated γ for T CH = 8, 10 and 12 nm, it has been observed that γ is the smallest for T CH = 8 nm which means that the electrostatic control on channel will be dominated by top gate. So, it can be stated that for a broad range of threshold regulation thicker channel is recommended. But, it has increased OFF-state current, so the tradeoff is inevitable. Also, Fig. 8 Fig. 9 (b) shows the γ comparison of BMF-SOI-JLFET with conventional tri-gate SOI-JLFET, and proposed device exhibits very large value of γ in contrast to SOI-JLFET thanks to the excellent coupling between BM and channel in BMF-SOI-JLFET.

C. Dynamic Threshold in BMF-SOI-JLFETs
To attain better S.S and enhanced ON-current without any added circuitry in MOSFETs, DT method has been developed. The electrical terminal of gate is tied to the body contact in the DT mode to change the V TH dynamically when the device becomes active (turned ON). The tied body works as secondary gate, i.e., pseudo-multigate [23], as it improves the controlling of gate electrostatic of device. In our proposed device, the gate is electrically tied to the buried metal. Here, BMF as secondary gate in this mode of operation will control the depletion of channel at bottom interface and during ON-state, device achieve atband condition fully as there is any depletion. But, in the OFF-state condition, BMF-SOI and gate contact are at same zero potential and therefore, current remains equal to OFF-state current in the mode when electrical contacts of gate and BM are untied. In ON-state, the barrier at BM-channel interface lowered signi cantly in DT compared to xed bias mode V BM =0 V as per Fig. 10(a) of the energy band diagram which results in enhanced carriers in channel as shown in Fig.   10(b). In contrast to the xed bias mode V BM =0 V, ON-current has been improved by 73% and Subthreshold Swing improved from 89.94 to 71.19 mV/dec in this mode. It is worth to mentioned that the improved performance in terms of ON-current and SS is achieved without scarifying OFF-state current.  In the previous section, we have seen variation in γ with T CH as large value of γ attributed to current gain.
ON-to-OFF current ratio decreases with increase in channel thickness T CH due to poor electrostatic control in thicker cannel as observed in Table 2 and Fig. 12 Table   3.

Conclusion
In this work, the numerical simulation of proposed BMF-SOI-JLFET is performed. The novel structure utilizes Schottky junction induced depletion which add-in greater gate controlling with adjusting parameters such as BMF bias and BM workfunction to improve its performance. We have analyzed its operation in multi threshold and DT modes by administering bias scheme on BMF. The BMF-SOI-JLFET exhibits a high γ value owing to robust integration of electrostatics uniformly between channel and BMF. Additionally, DT mode of operation offers a high and low V TH to achieve low leakage and high speed performance by virtue of improved I ON and S.S.