Design and Self-Consistent Schrodinger-Poisson Model Simulation of Ultra-Thin Si-Channel Nanowire FET

Since at the regime of nanometer, the quantum confinement effects are observed and the wave nature of electrons is more dominant. Therefore, the classical approach of current formulation in mesoelectonics and nanoelectronics results in inaccuracy as it does not consider the quantum effect, which is only applicable for the bulk electronic device. For accurate modeling and simulation of nanoelectronics, device atomic-level quantum mechanical models are required. In this work, an ultra-thin (2 nm diameter) Silicon- channel Cylindrical Nanowire FET (CNWFET) is designed and simulated by invoking non-equilibrium green function (NEGF) formalism and self-consistent Schrodinger-Poisson’s equation model. Then impact variation of temperature, oxide thickness, and metal work function variation in the NWFET is investigated to analyze the distinct performance parameters of the device e.g. threshold voltage (Vth) drain induced barrier lowering (DIBL), sub-threshold swing (SS), and ION/IOFF ratio. The designed device exhibits reliable results and shows a SS of 57.8 mV/decade and ION to IOFF ratio of order 109 at room temperature.


Introduction
The demand to scale down MOSFET to increase the chip density with high performance has forced the researcher to look for another device as MOSFET has reached its physical limit [1]. In 2010, Cheung et al., stated that the subthreshold swing of MOSFETs can never be below 60 mV/decade at room temperature [2]. The further scaling of the MOSFET channel roughly below 65 nm begins to exhibit quantum phenomena shows high leakage source to drain OFF current and control of gate is lost over the device [3][4][5]. Moreover, the limitation of the sub-threshold swing will lead to high leakage current even in the OFF state resulting in static power dissipation which finally may result in the thermal runway of the electronic device [6,7]. To maintain pace with Moore's Law and pack more and more transistors together, the researcher has been working beyond conventional semiconductor technology [8]. Since the main aim is a small-sized transistor with high performance and low power consumption, many changes in MOSFET structure and MOSFET-like structure were done and but with persistent short channel effects, the parasitic capacitance was observed and very little improvement in the subthreshold swing was achieved [9][10][11]. In case if the device succeeded in low SS then the ON/OFF current ratio was compromised. The novel Nanoscaled semiconductor devices like nanotube TFETs, Nanowire FET and CNTFET, etc. are very promising for future electronic systems [12][13][14]. But the study and simulation of the nanoscaled devices are challenging as at nanoscale regime, the transistor operates near the ballistic limit, electron-hole pairs are generated by the band to band tunneling despite thermal emission and show quantum effects [15,16].
The classical models of the simulation are optimal for the bulk device but for the mesoscopic and nanoscopic electronics devices, quantum mechanical models are required. Therefore, to include quantum confinement effects, the Self-consistent Schrodinger-Poisson model which uses the 1D NEGF method for computation of current is invoked and ultra-thin silicon channel cylindrical NWFET is designed by considering the nanowires to be a 1-D nanostructure. Then, the impact of work function variation, oxide thickness variation, and temperature variation are investigated to analyze device performance.

Device Design and Simulation Models
The 3D-designed structure of cylindrical nanowire FET (CNWFET) is shown in Fig. 1a. The diameter of the crosssection is chosen as 3 nm (2 nm Si + 1 nm SiO 2 ). The shown Fig. 1b is of the two-dimensional structure of the designed CNWFET which has been used for current simulation and is derived from cutting the three-dimensional structure along the Y-Z plane. The vertical length of the NWFET is 50 nm with a channel length of 30 nm and drain and source region length is 10 nm each. The source and drain are doped with an N-type uniform doping profile of 1 × 10 18 /cm 3 and1x10 20 /cm 3 whereas the channel is doped with a P-type doping profile of 1 × 10 15 /cm 3 . The various design parameters of the device are mentioned in Table 1.
Since the diameter of the designed device is 3 nm, it requires quantum mechanical models for its accurate simulation. The Self-consistent coupled Schrödinger Poisson model uses Schrodinger relation to obtain the density of state and Poisson equation to derive the potential which is further used in solving Schrödinger equations. There are few literatures available which support 3 nm diameter of the nanowire FETs [17,18]. Bangsaruntip et al., [18] designed a 25-stage ring oscillator using the gate all-around nanowire at the 3 nm node technology. The one-dimensional quantum confinement (say Y-axis), 1D Schrodinger Eq. (1) is used.
The Eq. (1) is solved to get Eigen state energies E iv (x)and wave function ψ iv (x, y) at each node perpendicular to X-axis.
Here, E C (x, y) is the band edge energy. The m v y x; y ð Þ represents effective mass in the Y direction and it should be noted these effective masses are dimension dependent and varies with the direction. The general Poisson equation is given by.
Where εis material-dependent permittivity, V is the electrostatic potential, and ρis the charge density. The density of state obtained by solving Eq. (1) are discrete and are reduced to a sum over bound state energies from integral over energy by applying Fermi-Dirac statistics. Thus the carrier concentrations obtained for 1D confinement is given as.
The evaluated carrier concentrations from Eq. (3) are substituted in net charge density in Poisson's relation. Since the net charge density is given by.
Where q is the absolute electron charge, N Doping is doping atom concentration in the Silicon film and N (x,y) is the calculated electron density. Thus, the potential derived from solving the Poisson Eq. (3) is substituted back into Schrodinger's equation. This is an iterative process between Schrodinger's and Poisson's equation which continues until convergence and a self-consistent solution of Schrodinger's and Poisson's equation is obtained. A predictor-corrector scheme using the non-equilibrium green function (NEGF) model is used for the stable and oscillation-less iteration process. After multiple iterations, wave functions are obtained and remain constant, where Eigen energies are constantly revised with each iteration and substituted in Poisson's equation. In this scheme, the Poisson equation act as a predictor, and the number of predictor iteration is controlled by the NEGF model.
The final solution of this self-consistent coupled Schrodinger-Poisson equation is incorporated in the driftdiffusion model (DDM) to obtain the current density and final drain current of the device. Equation (5) is a general driftdiffusion equation. The designed device is simulated in the atlas silvaco tool and during simulation drift-diffusion space model (dd_ms) along with Schrodinger (p.schro) and (ox. schro) are utilized to consider floating body effects and quantum confinements in cylindrical NWFET. Generationrecombination phenomena like Shockley-Read-Hall (srh), impact ionization, band to band tunneling and Auger models are also here.

Results and Discussions
To study the effect of various device design parameters on the performance of the device, drain current, electric field, Potential, are plotted through simulation. To analyze the impact of device design parameters on the performance of the device, the parameters such as silicon dioxide thickness (Tox), temperature, and gate work function are also varied.

A. Transfer and Output Characteristics
The transfer characteristics (I D -V GS ) of the cylindrical NWFET device including the design parameter mentioned in Table 1

B. Impact of Temperature Variation
To study the effect of temperature on the designed nanowire FET, the device is simulated at five different temperatures which are 273 K, 300 K, 310 K, 323 K, and 373 K. The obtained (I D -V GS ) characteristics, electric field, and potential variation at distinct temperatures are shown in Fig. 4. The uniform doping of source, drain, and the channel is maintained constant at 1 × 10 15 /cm 3 n-type, 1 × 10 20 /cm 3 n-type, and 1 × 10 15 /cm 3 p-type respectively. The effect temperature variation is highly observed on I OFF as with increasing temperature the OFF current increases but the I ON is very less affected by temperature variation. In Fig. 4b, it is observed that the temperature effect on the electric field is minimal and the potential curve tends to shift downward with increasing temperature as shown in Fig. 4c Table 2; these values are evaluated at the SiO 2 thickness of 1 nm, and gate work function of 4.7 eV. It can be seen from Table 2 that the threshold voltage and I ON /I OFF ratio decreases with the temperature whereas DIBL and SS increase with the temperature.

C. Silicon-Oxide (SiO2) Thickness Variation
To examine the impact of SiO 2 thickness variation on the device performance, the silicon oxide thickness is varied from 0.5 nm to 1 nm at constant room temperature and the corresponding I D -V GS characteristics, electric field variation, and potential variations are plotted in Fig. 5. It can be observed from the I D -V GS ) characteristics are shown in Fig. 5a that decreasing the oxide thickness increases both the I ON and I OFF but the increase is minimal. The doping concentration of source, drain, and channel regions are maintained constant at 1 × 10 15 /cm 3 n-type, 1 × 10 20 /cm 3 n-type, and 1 × 10 15 / cm 3 p-type respectively. The effect of SiO 2 thickness variation on device parameters such as potential and electric field is  shown in Fig. 5a and b which show augmentation in both electric field and surface potential of the device. The variations of the other performance parameters; V th , DIBL, SS, and I ON /I OFF ratio for various oxide thickness are summarized in Table 3, these values are evaluated at the gate work function of 4.5 eV and it is seen that I ON /I OFF ratio is the least for 1 nm SiO 2 thickness. And it is also noticed that the impact of SiO 2 thickness variation is negligible on the subthreshold swing but DIBL is significantly varying with varying SiO 2 thickness.

D. Metal-work Function Variation
The impact of metal work function on the various performance parameters of the NWFET at room temperature is plotted and summarized in Fig. 6 and Table 4 respectively, the doping concentration of source, drain, and the channel is maintained constant as stated before. The oxide thickness of 1 nm is maintained constant. From the I D -V GS characteristics graph shown in Fig. 6a, it is observed that changing the gate work function has enormous effects on device performance. The effect of metal work function variation on device parameters electric field and surface potential is shown in Fig. 6b and c respectively. The variations of the V th , DIBL, SS, and I ON /I OFF ratio for various oxide thicknesses are shown in   Table 4; these values are evaluated at room temperature. And it can be noticed that on increasing the metal work function both the electric field and surface potential reduce. A very low threshold voltage is observed at a low work function of 4.4 eV but as work function increases the threshold voltage also increases. The I OFF increases with increasing gate work function. The high I ON /I OFF ratio of order 10 9 is obtained at a work function of 4.7 eV. Further increasing the gate work function reduces the energy band bending and decreases the electric field. Due to increased I OFF with further increasing work function I ON /I OFF ratio reduces to an order of approximately 10 3 .

Conclusions
This paper presents the design and performance analysis of ultra-thin cylindrical NWFET. Here, the Self-consistent Schrodinger-Poisson model which uses the 1D NEGF (b) Fig. 6 Impact of the metal work function variation on the a ID-VGS characteristics b electric field c and potential methods for computation of current is invoked to model the quantum confinement effects, and then the 2-D Schrödinger equation is applied to the obtained current. Finally, the impact of temperature, oxide thickness, and metal-work function on various device performance parameters like threshold voltage, sub-threshold swing, DIBL, I ON /I OFF ratio is evaluated along with I D -V GS characteristics, electric field, and surface potential are investigated. The I ON at V GS = 1 V and V DS = 1 V is noticed as 6.70 × 10 −7 (A/μm) whereas the I OFF is observed as 5. 67 × 10 −16 (A/μm) and leads the I ON /I OFF ratio in the range of 10 9 . A 100 K rise in temperature from 273 K to 373 K causes an 8% decrement in V th, while 40% and 38% augment in DIBL and SS. The design shows a high I ON /I OFF ratio and hence will be very helpful in designing high-speed integrated circuits and ultra-thin sensor designing.
Author Contributions All authors have equally participated in the prep aring of the manuscript during implementation of ideas, findings result, and writing of the manuscript.
Data Availability Current submission does not contain the pool data of the manuscript but the data used in the manuscript will be provided on request.
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