SAT-Attack Resistant Hardware Obfuscation using Camouflaged Two-Dimensional Heterostructure Devices


 Reverse engineering (RE) is one of the major security threats to the semiconductor industry due to the involvement of untrustworthy parties in an increasingly globalized chip manufacturing supply chain [1-5]. RE efforts have already been successful in extracting device level functionalities from an integrated circuit (IC) with very limited resources [6]. Camouflaging is an obfuscation method that can thwart such RE [7-9]. Existing work on IC camouflaging primarily uses fabrication techniques such as doping and dummy contacts to hide the circuit structure or build cells that look alike but have different functionalities. While promising these Si complementary metal oxide semiconductor (CMOS) based obfuscation techniques adds significant area overhead and are successfully decamouflaged by the Satisfiability solver (SAT)-based reverse engineering techniques [9-13]. Emerging solutions, such as polymorphic gates based on giant spin Hall effect (GSHE) are promising but adds delay overhead in hybrid CMOS-GSHE designs restricting the camouflaging to a maximum of 15% of all the gates in the circuit. Here, we harness the unique properties of two-dimensional (2D) transition metal dichalcogenides (TMDs) including MoS2, MoSe2, MoTe2, WS2, and WSe2 and their optically transparent transition metal oxides (TMOs) to demonstrate novel area efficient camouflaging solutions that are resilient to SAT-attack and automatic test pattern generation (ATPG) attacks. We show that resistors with resistance values differing by 8 orders of magnitude, diodes with variable turn-on voltages and reverse saturation currents, and field effect transistors (FETs) with adjustable conduction type, threshold voltages and switching characteristics can be optically camouflaged to look exactly similar by engineering TMO/TMD heterostructures allowing hardware obfuscation of both digital and analog circuits. Since this 2D heterostructure devices family is intrinsically camouflaged, NAND/NOR/AND/OR gates in the circuit can be obfuscated with significantly less area overhead allowing 100% logic obfuscation compared to only 5% for CMOS-based camouflaging. Finally, we demonstrate that the largest benchmarking circuit from ISCAS’85, comprised of more than 4000 logic gates when obfuscated with the CMOS-based technique are successfully decamouflaged by SAT-attack in less than 40 minutes; whereas, it renders to be invulnerable even in more than 10 hours, when camouflaged with 2D heterostructure devices thereby corroborating our hypothesis of high resilience against RE. Our approach of connecting unique material properties to innovative devices to secure circuits can be considered as one of its kind demonstrations, highlighting the benefits of cross-layer optimization.

Camouflaging has emerged as a hardware obfuscation method that can thwart RE by hiding the functionality of a circuit. The inspiration is derived from nature, where countless animals camouflage themselves within their surroundings to conceal their presence from predators or catch unsuspecting preys. For example, Fig. 1a, appears to be the bark of a tree. However, a closer inspection reveals a camouflaged tree spider. Camouflaging adaptations have been proposed for ICs as shown in Fig. 1b. For an observer, the circuit functionality appears to be = , however, the true functionality is = , since the connection from the input to the output is camouflaged. IC camouflaging primarily involves fabrication of dummy contacts or threshold engineering through the alteration of channel doping [14][15][16][17][18] to make the circuits look alike but differ in functionalities. Gate netlist level camouflaging has also been proposed where camouflaging cells or camouflaging connections are inserted to maximize the resilience of the circuit netlist against RE techniques [13,19,20]. While innovative, these IC obfuscation techniques add significant area overhead and are easily decamouflaged when the reverse engineer launches SAT-attacks [9,10,13]. Furthermore, these obfuscation methods are based on the aging Si technology which is experiencing stagnation in energy, size, and complexity scaling [21,22] and at the same time does not offer low-cost, low-power, flexible, and printable solutions for the edge devices in the emerging era of Internet of Things (IoT) [23]. Finally, most of the proposed schemes have been implemented and tested at the simulation level with limited experimental demonstrations.
Here, we exploit unique material properties of two-dimensional (2D) transition-metal dichalcogenides (TMDs) and their corresponding transition metal oxides (TMOs) to obfuscate device and circuit level functionalities using TMO/TMD heterostructures as shown in Fig. 1c.
TMDs are layered compounds with strong in-plane covalent bonding and weak out-of-plane van der Waals (vdW) interaction which allows thinning of the material down to monolayer with thicknesses < 1 nm [24]. TMDs have the general formula of MX2, where M represents the transition metal atom, i.e. molybdenum (Mo) and tungsten (W) and X represents the chalcogen atom i.e. sulfur (S), selenium (Se), and tellurium (Te). Unlike, graphene which is a gapless 2D semimetal, TMDs offer finite bandgap in the range of 0.5 -3 eV making them promising candidates for post-Si nanoscale devices [25][26][27][28][29][30]. Note that even at atomically thin body thicknesses, TMDs are robust to detrimental quantum confinement effects observed in Si, which allows field effect transistors (FETs) based on mono or few-layers of TMDs to reinstate aggressive length scaling [31,32]. Moreover, the mechanical flexibility [33], optical transparency [34], and availability of TMD inks [35] make them attractive for IoT edge devices. Manufacturable solutions are also being developed through large area growth of TMDs using chemical vapor deposition (CVD) and other techniques [36]. TMOs on the other hand offer three unique properties: 1) TMOs are insulating in nature, 2) TMOs are optically transparent, and 3) TMOs are p-type dopants for TMDs [37][38][39]. Furthermore, when TMDs (MX2) are exposed to mild oxygen plasma, the top few layers can be transformed to corresponding sub-stoichiometric TMOs (MO3-y) through a selflimiting and highly anisotropic oxidation process that favors lateral oxidation within layers of MX2 with minimal vertical propagation [40][41][42]. This allows optical camouflaging of the TMO/TMD hetero-stack as shown schematically in Fig. 1d.
For experimental demonstration of optical camouflaging of TMO/TMD hetero-stack, WSe2 flakes were mechanically exfoliated on a 50nm alumina (Al2O3) substrate using the scotch-tape technique followed by imaging using an optical microscope. A random flake with a thickness ~ 35 nm, confirmed using an atomic force microscopy (AFM) was selected to analyze the impact of the oxygen plasma on its visual appearance. The flake was then sequentially exposed for the following time intervals: 15s, 30s, 75s, 120s, 210s and 300s to oxygen plasma at 50 watts RF power. Fig. 1e shows the images acquired between every exposure step. The minimum power setting needed to For an observer, the circuit functionality appears to be = , however, the true functionality is = , since the connection from the input to the output is camouflaged. c) Proposed camouflaging enabled by unique material properties of transition metal dichalcogenides (TMDs) and their corresponding transition metal oxides (TMOs). The optical image shows a camouflaged TMO/TMD hetero-stack device that can be either a resistor or a diode or a transistor. d) Schematic showing that when the TMDs are exposed to mild oxygen plasma, the top few layers can be transformed to corresponding sub-stoichiometric TMOs through a self-limiting and highly anisotropic oxidation process that favors lateral oxidation within layers of TMDs with minimal vertical propagation. TMOs are insulating, optically transparent and are p-type dopant for TMDs, whereas, TMDs are semiconducting, opaque, and intrinsically n-type. e) Optical images of a 35 nm thick WSe2 flake taken sequentially following exposer to mild oxygen plasma at 50 watts RF power for the indicated amount of times. f) Histograms of the red, green, and blue (RGB) color spectrum for the optical images in (e) show no significant changes in any of the three-color channels indicating that the images are practically indistinguishable. g) Color map of correlation coefficient (CC) between the binarized optical images from (e). CC values close to '1' indicate perfect similarity between the images. These findings suggest that the plasma treatment process and hence the presence of TMO on top of the TMD is concealed from the adversary. Furthermore, the thickness of the TMO layer, which depends on the plasma exposure time, as well as the region of its presence (i.e. partial or complete covering of the TMD) are also not revealed in the optical images. generate a stable plasma was used for the plasma etch tool to minimize physical damage to the 2D flakes and also to establish a reliable, controllable and reproducible method for obtaining the TMO/TMD hetero-stack (see Method sections for details). Fig. 1f shows the histogram of the red, green, and blue (RGB) color spectrum in the optical images of the WSe2 flake corresponding to different plasma exposure times. Clearly, there is no significant changes in any of the three-color channels indicating that the images are practically indistinguishable. Furthermore, Fig. 1g shows the color map of the correlation coefficient (CC) between the binarized optical images from Fig.   1e. The binarization was done using standard MATLAB coding. A CC value of '1' indicates perfect similarity between the images, whereas '0' indicates that the images are completely different. CC values in Fig. 1g are found to be near 1 with a mean ~ 0.85, which ensures that the plasma treatment process and hence the presence of TMO on top of the TMD is concealed from the adversary (see Supplementary Information 1 for camouflaged TMO/TMD hetero-stack of various thicknesses). Furthermore, the thickness of the TMO layer, which depends on the plasma exposure time, as well as the region of its presence (i.e. partial or complete covering of the TMD), are also not revealed in the optical images. However, as we will describe next, such camouflaged and lithographically patterned TMO/TMD hetero-stacks offer a wide range of device functionalities, which can revolutionize hardware obfuscation to prevent RE efforts without adding any area or energy overhead that makes it attractive for smart and secure technologies of the future. Fig. 2a shows the schematic of a camouflaged resistor based on TMO/TMD hetero-stack, whose resistance value can be adjusted in three possible ways: 1) by controlling the oxygen plasma exposure time, 2) by using different TMD flake thicknesses and 3) by changing the TMD material. Fig. 2b shows the optical images of a camouflaged resistor based on 10 nm thick WO3-y/WSe2 hetero-stack before and after 30s of oxygen plasma exposure and Fig.   2c shows the corresponding current versus voltage characteristics. The change in resistance of the stack is attributed to the change in the surface charge doping introduced by the sub-stoichiometric WO3-y in the underlying WSe2. The oxygen deficient WO3-y captures electron from intrinsic WSe2 and thereby moves the equilibrium Fermi level close to the valence band resulting in p-type doping of WSe2 as shown using the energy band diagrams in Fig. 2d. Fig. 2e shows the bar plot for the extracted resistance values for camouflaged WO3-y/WSe2 hetero-stack resistors for different initial thicknesses of the exfoliated WSe2 flakes as a function of plasma exposure time. Note that the current is normalized to the width of the resistor and hence the resistance values are indicated in Ω-µm. All resistors had 1µm channel length and 40 nm Ni/ 30 nm Au as the contact metal. The resistance value changes by more than 8 orders of magnitude without changing the device footprint and at the same time remains optically indistinguishable. The non-monotonic trend in the resistance values for the thinner flakes can be attributed to the fact that thin WSe2 flakes are found to be intrinsically n-type doped (low resistance). Short plasma exposure times induce p-type doping through sub-stoichiometric WO3-y, which compensates for the n-type doping and makes the stack intrinsic (high resistance). With continued plasma exposure, p-type doping keeps increasing and the stack becomes more conductive (low resistance). On the other hand, thicker WSe2 flakes are more intrinsic (high resistance) in nature and therefore show monotonic decrease in resistance with increased plasma exposure time. Finally, Fig. 2f-i show the bar plot for extracted resistance values for representative thin and thick MoS2, MoSe2, MoTe2 and WS2 based camouflaged resistors pre-and post-exposure to oxygen plasma for 75s. The increase in resistance for post-plasma treated MoS2, MoSe2, and WS2 is due to the fact that all of these materials exhibit intrinsic n-type doping which is compensated by the p-type doping introduced by their corresponding sub-stoichiometric oxides irrespective of the thickness. On the contrary, post plasma treated MoTe2 stack shows decrease in resistance, similar to WSe2 owing to the lack of any intrinsic n-type doping. The resistance values are also impacted by the Schottky barrier (SB) that exists at the metal/TMD interface [43,44]. For Schottky injection, the barrier height and width play a critical role in determining the contact resistance. The barrier height depends on the choice of metal, position of metal Fermi level pinning, pinning factor etc. and barrier width is determined by the flake thickness and doping [45]. Nevertheless, for any given TMD and for any choice of based camouflaged resistors pre-and post-exposure to oxygen plasma for 75s. While any semiconducting material will form insulating and transparent surface oxide when exposed to mild oxygen plasma, what makes TMOs unique is their capability to dope the underlying TMDs and thereby change the resistance values by orders of magnitude. These TMO/TMD hetero-stack resistors can, therefore, be used to camouflage connections between devices and circuits in an IC to increase the complexity of RE without adding any area or energy overhead. thickness, it is possible to achieve orders of magnitude difference in the resistance values in the TMO/TMD hetero-stack resistors through controlled oxygen plasma treatment without compromising their optical indistinguishability which is the key for the success of resistance camouflaging against RE efforts. While most semiconducting materials will form insulating and transparent surface oxides when exposed to mild oxygen plasma, what makes TMOs unique is their capability to dope the underlying TMDs and thereby change the resistance values by orders of magnitude. These TMO/TMD hetero-stack resistors can, therefore, be used to camouflage connections between devices and circuits in an IC to increase the complexity of RE without adding any area or energy overhead.

Camouflaged Resistors:
Camouflaged Diodes: Diodes are non-linear passive components essential for any IC design. Both analog and digital circuits require diodes. Therefore, camouflaged diodes can add significant challenge to any RE effort. Fig. 3a shows the schematic of a camouflaged diode based on TMO/TMD hetero-stack. Camouflaged diodes require an additional processing step where one side of the fabricated WSe2 resistors are protected by PMMA which is patterned using electron beam lithography before exposure to the oxygen plasma (see Method sections for details). The PMMA is striped off afterwards. This fabrication step ensures that the protected area remains intrinsic, whereas the exposed area becomes p-type due to the formation of sub-stoichiometric MO3-y. Fig. 3b shows the optical images of the device before and after the fabrication of the diode based on WSe2. Clearly, the images appear identical making it difficult for an adversary to recognize the functionality of the device through visual inspection. Fig. 3c-f show the current versus voltage characteristics of a thin and a thick diode in linear and logarithmic scales, respectively. These plots show rectifying behaviors. Since the diodes were fabricated on a back-gate stack comprised of 50 nm Al2O3 as the back-gate oxide and Pt/TiN/p ++ -Si as the back-gate electrode (Fig. 3a), dynamic reconfiguration of the diode characteristics is possible through electrostatic doping using the back-gate voltage ( ). Supplementary Information 2 shows the tunability in diode turn on voltage and reverse saturation current using for thin and thick WO3y/WSe2 stacks. The thin diode (Fig. 3c) shows late turn on since the built-in-potential is higher between the undoped region which is intrinsically n-type doped and the p-type doped region  compared to the thick diode (Fig. 3e) where the undoped region is more intrinsic. Also note that the thin diode offers significantly lower reverse saturation current (Fig. 3d), whereas, the reverse saturation current depends strongly on the applied for the thick diode (Fig. 3f). This is expected, since for thicker diodes, the phenomenon of Thomas-Fermi charge screening restricts the doping effect to only top few layers [46], while the layers at the bottom of the stack i.e. the layers close to the oxide are under firm back-gate control. For ≫ 0, these layers become electrostatically n-doped and offer a parallel conduction path for the current to flow between the two metal contacts. The tunability of camouflaged diode characteristics through back-gating adds one more level of complexity to RE.   ON/OFF ratio. Since gating in our devices occur form the back, for thicker flakes the p-type channel near the top surface is weakly modulated by the back-gate voltage and hence continues to conduct significant amount of current even in the OFF state resulting in lower ON/OFF current ratio. However, in thinner flakes, the back-gate can fully compensate the p-type doping induced by the surface charge due to better electrostatic control which allows the device to reach lower OFF state current and hence higher current ON-OFF ratio. Finally, Fig. 4g-j show the transfer characteristics for representative MoS2, MoSe2, MoTe2, and WS2 based camouflaged FETs before and after exposure to oxygen plasma for 75s. It is clear that irrespective of the choice of material, p-type conduction is enhanced. For MoS2 FET (Fig. 4g), the electron conduction dominates even after 75s of plasma exposure. This is due to that fact that MoS2 shows a high level of intrinsic ntype doping, which is evident from the large negative threshold voltage seen in its pre-plasma treatment characteristics. Furthermore, the phenomenon of metal Fermi level pinning close to the conduction band of MoS2 facilitates easier electron injection and limits hole conduction [45]. For Nevertheless, TMD FETs can be camouflaged with tunable device parameters through oxygen plasma exposure irrespective of their thickness and composition and without compromising their optical indistinguishability which is critical for defying the RE efforts. What is more attractive is that these camouflaged TMO/TMD hetero-stack devices do not add any area overhead which is unavoidable for the state-of-the-art layout level camouflaging approaches.

Camouflaged Circuits and Logic Gates:
In conventional digital and analog circuit designs the basic hardware elements such as resistor, diode, n-type, and p-type FETs have unique footprints, which allow the adversary to seamlessly identify the devices through optical inspection and thereby reconstruct the circuit functionality. State-of-the-art camouflaging approaches prevent such RE effort by introducing dummy contacts which increases the area overhead. However, our camouflaged resistors, diodes, and FETs are optically indistinguishable since their layouts are identical making the RE through visual inspection to be futile. In this case, the reverse engineer has to adopt a trial and error approach to identify the circuit functionality. If there are hardware components in an IC, each with possibilities, the number of trials will be equal to the number of unique functionalities ( ), which will be given by, = . Fig. 5a shows the number of RE trials as a function of and , which becomes astronomical when one considers billions of camouflaged devices on a chip, each with many possibilities, i.e. resistance values that differs by more than 8 orders of magnitude for camouflaged resistors, turn on voltages and reverse saturation current that can be adjusted for camouflaged diodes, and conduction type, threshold voltage, current ON-OFF ratio, etc. that can be tuned for camouflaged FETs. Even for relatively small, = 1000 and = 6, the number of RE trials become = 10 40 . Fig. 5b shows the layout of a camouflaged analog circuit.
Here both layouts are visually identical but the one functions as a voltage divider, while the other functions as a half-wave rectifier. Similarly, Fig. 5c shows a camouflaged digital to analog mapping circuit with multiple digital input and one analog output. This circuit functions as a digital to analog converter (DAC) for 1 2 � = 2, but transforms into a digital bit counter (DBC) that counts the number of ones in a digital sequence for 1 2 � ≫ 2.
Next, we show that conventional combinational logic gates -NAND, NOR, AND, and OR can be camouflaged using 2D heterostructure device-based circuit elements, thereby obfuscating the gate functionality. Fig. 6a models the template of the camouflaged representation of a logic circuit, where each boxed element can be either a p-type FET or an n-type FET or a resistor. Different instances of these camouflaged elements are mapped onto a box of the model circuit to devise multi-functional logic gates. The realization of NAND gate operation based on CMOS logic is shown in Fig. 6b. The corresponding representations of AND, NOR and OR gates are shown in

Resilience to SAT-Attack:
To analyze the prowess of our proposed circuit level camouflaging scheme, these visually identical logic gates are employed to camouflage the ISCAS'85 benchmark circuits. The ISCAS'85 benchmark suite is comprised of 11 circuits with multi-input gates from multiple logic families, which is traditionally used by existing research to evaluate their proposed camouflaging schemes [9,11,12]. Each circuit has been decomposed into two-input gates. All the NAND, NOR, AND, and OR gates in the circuit are then camouflaged according to the respective camouflaging techniques as discussed, and the cumulative increase in area overhead incurred to accommodate the camouflaged gates is calculated for each circuit.  [10]. Each of the obfuscated netlist from the ISCAS'85 benchmark is executed on the SAT-solver for more than 10 hours.
Although the SAT-attack is successful in breaking the c17 and c432 benchmark, the other nine benchmarks are resilient against the attack, even with inexhaustive resource space. The resilience of the proposed camouflaging approach is compared with state-of-the-art circuit obfuscation scheme in CMOS-based implementations [9,10]. The two largest benchmarks, c5315 and c7552 when obfuscated with the CMOS-based technique are successfully decamouflaged by SAT-attack in less than 40 minutes, whereas, these benchmarks render to be unbreakable even in more than 10 hours, when camouflaged with 2D heterostructure devices. Since the largest benchmarks are vulnerable to SAT-attacks under CMOS-based obfuscation, it can be inferred that the benchmarks with lower gate counts can also be easily decamouflaged in lesser amounts of time. However, smaller benchmarks camouflaged with the proposed obfuscation scheme exhibit to be unbreakable, even with extensive resource space, as shown in Table 1. Since the benchmarks in ISCAS'85 manifest strong resiliency to SAT-attacks, we restrict ourselves from analyzing larger benchmarks attacks. Given an obfuscated netlist, an attacker, with the ATPG tool, generates a set of input patterns to the black-box circuit. Following this, the adversary aims to resolve the camouflaged gates by analyzing the corresponding output patterns from the circuit. Resolving an unknown logic gate involves two steps -activation and propagation. In order to activate a particular logic gate, at least one of the two inputs should be controllable. Either the gate should be controlled by primary inputs or by resolved/non-camouflaged gates in the fan-in cone that are controlled by the primary inputs. Subsequently, the tool aims to propagate the output of this missing gate to one of the primary outputs through a clean path in its fan-out cone. A clean path is defined as a path that is not passing through any other missing gate. An analysis of the observable outputs after a successful activation and propagation aids the adversary in resolving each camouflaged gate in the logic circuit. The ATPG attack is launched on each of the camouflaged netlist from the ISCAS'85 benchmarks. Owing to a successful obfuscation of all the NAND, NOR, AND and OR gates in each circuit by our proposed camouflaging scheme, the ATPG tool fails to execute the activation and propagation operation. As a result, the ATPG attack is incapable of breaking any of the benchmark circuits. Even the smallest benchmark, c17 is resilient against the ATPG attack, the obfuscated netlist of which is demonstrated in Figure 7. Although gate G4 can be activated by the primary input E, the fan-out cone is devoid of a clean path to propagate to any of the observable outputs. On the contrary, gate G6 despite having a clean path to the primary output Y2 contains missing gates in its fan-in cone. Hence, G6 cannot be activated by any of the primary inputs and therefore, cannot be resolved by the adversary. Thus, the proposed obfuscation scheme proves to be strongly resilient against ATPG attacks, thereby bolstering the security of the camouflaged circuits against reverse engineering.

Comparative Analysis between Polymorphic Spin-Hall Effect Devices and 2D Heterostructure
Devices: Among the emerging devices that offer to enhance hardware security, polymorphic gates OR, NAND, NOR, XOR, XNOR, NOT and BUF [49]. However, due to the formidable delay overhead of the GHSE switch arising in hybrid CMOS-GSHE designs, camouflaging is restricted to a maximum of 15% of all the gates in the circuit. On the contrary, we implement all the logic gates in a circuit with 2D heterostructure devices, thereby eliminating the need for a hybrid design.
As a result, our proposed camouflaging technique with these devices is capable to obfuscate 100% of all the possible gates that can be camouflaged in the circuit.  Optical Decamouflaging Approaches: Simple RE efforts such as mechanical delayering followed by optical imaging to recognize the hardware elements will be unsuccessful for camouflaged 2D material-based devices and circuits. If the reverse engineer has access to advance instrumentations such as parameter analyzers, signal generators, oscilloscopes etc., then it is possible to identify the circuit functionality through electrical probing of key connections. However, most of these connections are made using narrow metallic interconnects with dimensions less than 100nm making it challenging to access even using advanced micro probe technologies. A reverse engineering attacker with access to advanced characterization tools such as SEM, AFM, and Raman may be able to gather some critical information. For example, Fig. 8a shows the SEM images of a WSe2 based TMO/TMD hetero-stack device before and after the exposure to the oxygen plasma. The two channels look remarkably similar, however, on a closer look, one can observe slight alterations of the surface due to mild physical damage of the flake introduced by the plasma. While the SEM image indicates additional processing of the channel, it does not reveal any information regarding the thickness and composition of the 2D material, plasma type, exposure time, and the pattern design that determines if the device is a resistor or a diode or a transistor. The flake thickness can be measured using AFM as shown in Fig. 8b for a representative WSe2 flake.
The height histograms in Fig. 8c show few nanometers decrease in the flake thickness following 300s of oxygen plasma exposure. However, without having any knowledge of pre-plasma exposure flake thickness, the reverse engineer is unlikely to extract any meaningful information about the device functionality from the AFM image. Finally, Fig. 8d shows the Raman spectroscopy of a 10nm thick WSe2 flake using the 532nm ULF laser before and after 300s of Reverse engineer with access to even more advanced tools such as TEM and energy dispersive Xray spectroscopy (EDS) can obtain the elemental information and precise thicknesses of the TMD and TMO in the device stack from the cross-section imaging. While the above-mentioned characterization techniques are powerful for decamouflaging a single device, they are mostly non scalable to billions of devices on a chip. As such the RE risk will remain significantly low for TMO/TMD hetero-stack camouflaged devices and circuits.
In the conclusion, we have successfully demonstrated a novel camouflaging technique that allows obfuscation of logic gates and benchmarking circuits with unprecedented area efficiency and

Methods
Device Fabrication: Multilayer TMD flakes were mechanically exfoliated on a 50nm alumina substrate. The transferred flakes were mapped in terms of their location and dimensions using an optical microscope. The plasma doping was performed in a Tepla M4L plasma etching tool. Before placing the sample inside the tool, a conditioning step was performed to prepare the chamber. The radiofrequency (RF) power was set to 300 W and the pressure inside was set to 500-mTorr. The O2 and He flow rates were adjusted to 150 and 50 standard cubic centimeters (sccm) respectively and the conditioning was done for 5 minutes. For doping the flakes, the chamber pressure and gas flow rates were set to the same values with the RF power adjusted to 50W. These conditions represent the minimum power and gas flow rates for a reliable and consistent plasma in this particular tool. The RF power was kept at a minimum to mitigate any damaging effects to the flake.
Various WSe2 flakes with a mean thickness ranging from 8nm to 45nm were selected and subsequently exposed to the oxygen plasma for varying time intervals of 15s, 30s, 75s, 120s, 210s and 300s. Optical images were acquired between each time step using a Nikon L200ND microscope with a 100x lens objective and the flake thicknesses were measured prior to and after 300s of exposure with atomic force microscopy (AFM) to observe any visible changes in their appearances and thickness reduction respectively as a result of prolonged plasma exposure. For defining the contacts, the substrate was first spin-coated with MMA/PMMA bilayer stack, and electron-beam lithography (EBPG 5200 Vistec e-beam with Raith software) was used to pattern the source and drain pads. The exposed PMMA was removed using a 1:1 methyl isobutyl ketone and isopropanol (MIBK: IPA) developer. Thereafter, 40 nm Ni/30 nm Au metal stack was deposited at the rate of 2 Å/s using the Temescal FC2000 metal evaporator. A second lithography step was performed where the flakes were exposed for subsequent plasma doping and form a WSe2/WO3-y hetero-stack. For the resistance and transistor camouflaging, the entire flake region along the channel length and width was exposed whereas for diode camouflaging, half of the region was kept protected by the PMMA resist and the other half was exposed to the plasma. The total exposure time was 75s for all the five different TMDs and the devices were characterized electrically both before and after the plasma using a Keysight B1500A parameter analyzer in a lakeshore CRX-VF probe station. The excess PMMA was finally stripped off using standard liftoff procedure in acetone and IPA for the final optical imaging.
Electrical Measurements: Electrical measurements were performed in air inside a Lakeshore probe station using a B1500A Keysight semiconductor parameter analyzer.
Data Availability: The datasets generated during and/or analyzed during the current study are available from the corresponding author on reasonable request.
Code Availability: The codes used for plotting the data are available from the corresponding authors on reasonable request.     is more attractive is that these camouflaged TMO/TMD hetero-stack devices do not add any area overhead which is unavoidable for the state-of-the-art layout level camouflaging approaches.    nanometers decrease in the flake thickness following 300s of oxygen plasma exposure. However, without having any prior knowledge of the pre-plasma exposure flake thickness, the reverse engineer is unlikely to extract any meaningful information about the device functionality from the AFM image. Raman spectroscopy (d) shows small observable shift in the 2 1 mode, which can be attributed to the lateral oxidation of the flake and can be used for RE. While the above-mentioned characterization techniques are powerful for decamouflaging a single device, they are mostly non scalable to billions of devices on a chip. As such the RE risk will remain significantly low for TMO/TMD hetero-stack camouflaged devices and circuits. Figure 1 Camou aged two-dimensional (2D) heterostructure for hardware obfuscation. a) Natural camou aging for survival. Photograph of a camou aged tree spider. b) IC camou aging using dummy contact to thwart reverse engineering. For an observer, the circuit functionality appears to be = , however, the true functionality is =, since the connection from the input to the output is camou aged. c) Proposed camou aging enabled by unique material properties of transition metal dichalcogenides (TMDs) and their corresponding transition metal oxides (TMOs). The optical image shows a camou aged TMO/TMD hetero-stack device that can be either a resistor or a diode or a transistor. d)

Figures
Schematic showing that when the TMDs are exposed to mild oxygen plasma, the top few layers can be transformed to corresponding sub-stoichiometric TMOs through a self-limiting and highly anisotropic oxidation process that favors lateral oxidation within layers of TMDs with minimal vertical propagation. TMOs are insulating, optically transparent and are p-type dopant for TMDs, whereas, TMDs are semiconducting, opaque, and intrinsically n-type. e) Optical images of a 35 nm thick WSe2 ake taken sequentially following exposer to mild oxygen plasma at 50 watts RF power for the indicated amount of times. f) Histograms of the red, green, and blue (RGB) color spectrum for the optical images in (e) show no signi cant changes in any of the three-color channels indicating that the images are practically indistinguishable. g) Color map of correlation coe cient (CC) between the binarized optical images from (e). CC values close to '1' indicate perfect similarity between the images. These ndings suggest that the plasma treatment process and hence the presence of TMO on top of the TMD is concealed from the adversary. Furthermore, the thickness of the TMO layer, which depends on the plasma exposure time, as well as the region of its presence (i.e. partial or complete covering of the TMD) are also not revealed in the optical images. semiconducting material will form insulating and transparent surface oxide when exposed to mild oxygen plasma, what makes TMOs unique is their capability to dope the underlying TMDs and thereby change the resistance values by orders of magnitude. These TMO/TMD hetero-stack resistors can, therefore, be used to camou age connections between devices and circuits in an IC to increase the complexity of RE without adding any area or energy overhead.

Figure 3
Camou aged Diodes. a) Schematic of a camou aged diode based on TMO/TMD hetero-stack. Camou aged diodes require an additional processing step where one side of the fabricated TMD resistors are protected by PMMA which is patterned using electron beam lithography before exposure to the oxygen plasma. The PMMA is striped off afterwards. This fabrication step ensures that the protected area remains intrinsic, whereas the exposed area becomes p-type doped due to the formation of substoichiometric TMO. b) Optical images of the device before and after the fabrication of the diode based on WSe2. Clearly, the images appear identical making it di cult for an adversary to recognize the functionality of the device through visual inspection. Current versus voltage characteristics of a thin diode in c) linear and d) logarithmic scales. Clearly, rectifying behaviors are observed. Since the diodes were fabricated on a back-gate stack comprising of 50 nm Al2O3 as the back-gate oxide and Pt/TiN/p++-Si as the back-gate electrode, dynamic recon guration of the diode characteristics is possible through electrostatic doping using the back-gate voltage (). Current versus voltage characteristics of a thick diode in e) linear and f) logarithmic scales. The thin diode shows late turn on since the built-in-potential is higher between the undoped region which is intrinsically n-type doped and the p-type doped region compared to the thick diode where the undoped region is more intrinsic. Also, the thin diode offers signi cantly low reverse saturation current, whereas, the reverse saturation current depends strongly on the applied for the thick diode. This is expected since for thicker diodes, the phenomenon of Thomas-Fermi charge screening restricts the doping effect to only top few layers, while the layers at the bottom of the stack i.e. the layers close to the oxide are under rm back-gate control. For 0, these layers become electrostatically n-doped and offer a parallel conduction path for the current to ow between the two metal contacts. The tunability of camou aged diode characteristics through back-gating adds one more level of complexity to RE.

Figure 4
Camou aged Transistors: a) Schematic of a camou aged FET based on TMO/TMD hetero-stack. b) Optical images of WO3-y/WSe2 hetero-stack FET before and after the oxygen plasma exposure. Clearly, the images appear identical making it di cult for an adversary to recognize the FET functionality through visual inspection. c) Evolution of the transfer characteristics for WO3-y/WSe2 hetero-stack FET as a function of oxygen plasma exposure time for two different initial ake thicknesses. d) A table summarizing the transition of pristine WSe2 based FETs from dominant n-type to ambipolar to p-type transport characteristics as the plasma exposure time increases for various ake thicknesses. The change in dominant carrier transport from electron conduction (n-type) to hole conduction (p-type) with increasing plasma exposure time is consistent with the fact that the sub-stoichiometric WO3-x introduces p-type doping in the underlying WSe2. Color map for e) threshold voltages () and f) current ON/OFF ratio for the dominant branch. Similar observations can be made in the transfer characteristics of g) MoS2, h) MoSe2, i) MoTe2 and j) WS2 based camou aged FETs before and after exposure to oxygen plasma for 75s. Irrespective of the choice of material, p-type conduction is enhanced. These results indicate that TMO/TMD hetero-stack FETs can be camou aged with tunable device parameters through oxygen plasma exposure irrespective of their thickness and composition and without compromising their optical indistinguishability which is critical for defying the RE efforts. What is more attractive is that these camou aged TMO/TMD hetero-stack devices do not add any area overhead which is unavoidable for the state-of-the-art layout level camou aging approaches Figure 5 Camou aged analog circuits. a) Number of trials () for reverse engineering an integrated circuit (IC) with hardware components, each with possibilities. Even for relatively small, = 1000 and = 6, the number of RE trials becomes astronomical, = 1040. b) Camou aged circuit layout exploiting TMO/TMD hetero-stack devices. Both layouts are visually identical but the one functions as a voltage divider, while the other functions as a half wave recti er. c) A camou aged digital to analog mapping circuit with multiple digital input and one analog output. This circuit functions as a digital to analog converter (DAC) for 12 =2 transforms into a digital bit counter (DBC) that counts the number of ones in a digital sequence for 12 2. Camou aged logic gates. a) Overview of a digital logic circuit with camou aged elements. Actualization of b) NAND gate, c) AND gate, d) NOR gate, and e) OR gate with TMO/TMD hetero-stack based camou aged p-FET, n-FET, and resistor. Since the camou aged devices are physically identical to each other, the gates developed using those elements also look the same.

Figure 7
Camou aged digital circuit. The c17 benchmark circuit consisting of 6 camou aged gates (G1 to G6), in order to demonstrate resilience against ATPG attacks.

Figure 8
Optical decamou aging solutions. a) SEM images, b) AFM images, c) AFM height histograms, and d) Raman measurements of a WSe2 based TMO/TMD hetero-stack device before and after the exposure to the oxygen plasma. In the SEM image the two channels look remarkably similar, however, on a closer look, one can observe slight alterations of the surface due to mild physical damage of the ake introduced by the plasma. While the SEM image indicates additional processing of the channel, it does not reveal any information regarding the thickness and composition of the 2D material, plasma type and exposure time, and the pattern design that determines if the device is a resistor or a diode or a transistor. The height histograms (c) show few nanometers decrease in the ake thickness following 300s of oxygen plasma exposure. However, without having any prior knowledge of the pre-plasma exposure ake thickness, the reverse engineer is unlikely to extract any meaningful information about the device functionality from the AFM image. Raman spectroscopy (d) shows small observable shift in the 21 mode, which can be attributed to the lateral oxidation of the ake and can be used for RE. While the above-mentioned characterization techniques are powerful for decamou aging a single device, they are mostly non scalable to billions of devices on a chip. As such the RE risk will remain signi cantly low for TMO/TMD hetero-stack camou aged devices and circuits.

Supplementary Files
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