Overlapped Gate-Source/Drain H-shaped TFET: Proposal, Design and Linearity Analysis

In this paper, the proposed design of H-shaped TFET has been discussed. This design is providing a high Ion/Ioff ratio with a better Ion. HfO2 is used for better tunnelling current. The controllability of gate voltage on the drain current improves as the gate area increases. We can obtain better outcomes for current in this design by altering the architecture. With this device, Different parameters such as unit parameter, analog parameter, and linearity parameter have been studied and investigated the output of the H-TFET. As unit parameters, the electric field, electric potential, energy band diagram, and non-local band-to-band tunnelling rate (BTBT) have all been observed. Second and third-order harmonics distortion (HD2, HD3), third-order current intercept point (IIP3), third-order intermodulation distortions (IMD3), and second and third-order voltage intercept point (VIP2, VIP3) are evaluated as linearity parameters that characterize the device’s distortions and linearity. We obtained Ion=1.6x10−4\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$${\text{=1.6x}10}^{-4}$$\end{document} A/μm,Ioff=2.1x10−19\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$${\text{x}10}^{-19}$$\end{document} A/μm, Ion/Ioff=7.6x1014\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$${\text{x}10}^{14}$$\end{document},threshold voltage Vt=0.3449 V. © 2017 ElsevierInc.Allrightsreserved.


Introduction
We all required a device which has low power consumption, high speed and low area. This requirement is done by scaling of device. Scaling below nanoscale has some drawbacks ex. high power dissipation, short channel effect (SCE) [1]. So, we need a device which have less effected from SCE. Scaling the supply voltage in the case of MOSFETs will reduce power consumption [2]. The effective voltage determines the drain to source current, which can be improved by scaling the threshold voltage. The leakage current increases exponentially as the threshold voltage (Vth) is scaled up [3].Owing to the inability to scale the subthreshold swing (SS) under the Boltzmann limit of 60 mV/decade at room temperature [4], the physical geometry of the devices is quickly scaled down, but the power supply of the devices is not scaled down in the very same manner [3]. To address the shortcomings of traditional MOSFETs, a new operating theory has been tested using a particular kind of transistor construction, non-silicon-based materials [3]. So we take TFET for that which has a good Ion /Ioff [5] ratio with low subthreshold swing. Because of the band-to-band tunnelling (BTBT) process in TFETs, they have a lower ON-current (Ion) than traditional MOSFETs [1]. Low Ion, high SSavg, high Vt, small Ion/Ioff, ambipolar currents, and drain driven current improvement due to large silicon bandgap are all disadvantages of standard Si-TFETs [6,7]. Nanotube TFETs have good RF performance. In respect of drive current capacity, energy loss, and area, the NT structure is superior [8,9].However, if it is to be used in digital devices, the reverse gate bias condition, i.e. ambipolar current, must be reduced [10]. Due to indirect bandgap [6] semiconductor and scattering phenomena, the band-to-band tunnelling (BTBT) efficiency in silicon is lower. The current in a MOSFET [1] is measured by the thermionic emission of free charge carriers.
But it is primarily from BTBT in TFET [5].
Here from the above Eq. (2), we understand that the bandto-band tunneling (BTBT) current is exponentially dependent on electric field. Different novel architectures [11], such as dual gate architecture TFETs, have been developed to enhance the existing drive capabilities (I on ) of TFETs [1]. For the improvement in current in TFET, we use different types of structures and architectures of TFET, H-shaped TFET is also one of those structure. The current in TFET is mainly dependent on band to band tunneling current.

Device Structure and Simulation Parameters
The proposed structure of Overlapped gate-source/drain Hshaped TFET is shown in Fig. 1. In this design, we have gate is surrounded by channel for more tunneling. Gate is controlling tunneling in both directions. Tunneling is occurring in vertical direction. HfO 2 [12] is used instead of SiO 2 for better I off current. When a gate voltage is applied, electrons are start tunneling from source to channel. Gate is overlapped by the channel. Overlapped area by gate on channel is responsible for the controllability of gate and hence it affects the tunneling rate of carriers.
The doping parameters for this device for different sections are shown in Table 1. We take heavily doped p + source for enhancing I on current, with lightly doped p-channel and moderately doped n + drain to reduce leakage current. The gate electrode work function is about 4.5 eV. The device parameters channel thickness (w c ), source/drain thickness and gate oxide thickness (t ox ), Source/drain length (L S /L D ), channel length (L C ) are shown in Table 1.
We use ATLAS Silvaco TCAD tool for the simulation of this design [13]. The tunnelling current for a degenerated P-N junction can be correctly modelled using the non-local BTBT approach in both forward and reverse bias conditions. In the "MODEL" sentence, we used "BBT.NONLOCAL" to allow this model. In addition to the "BBT.NONLOCAL" parameter being defined in the "MODEL" argument, in the region containing a single P-N junction, where quantum tunnelling is required, a mesh must be specified. The non-local BTBT model depicts correct charge carrier tunnelling [14] in the system, with tunnelling occurring at the Source-Channel interface. For proper tunnelling, fine (light) meshing is needed at the Source-Channel interface. At the Source-Channel terminal, quantum meshing (qt mesh) is also performed. For proper tunnelling, the effective mass of an electron is taken 0.22me and the effective mass of a hole is 0.12mh [13]. Quantum meshing is carried out in both the x and y directions. In Fermi -Dirac carrier diffusion equations, the Fermi formula is used.

Simulation Results and Discussion
The exact type of behaviour of H-TFET can be seen in device parameters like electron/hole concentration, electric field variation, potential variation energy band diagram, and nonlocal band to band tunnelling rate (BTBT).
It is obvious that no tunnelling is feasible in the OFF state, so Ioff is very weak, while tunnelling is possible in the ON  state. In Fig. 2(a), energy band diagram [15] is shown which describes where the tunnelling is possible. At VDS = 0.5 V. The OFF state [VDS > 0 V and VGS = 0 V] is seen in red, while the ON state [VDS > 0 V and VGS > 0 V] is seen in blue. Caused by the sudden transition in the doping profile from the source to the channel area, the electric field is high [16].
Tunnelling range is larger in the OFF state than it is in the ON state. As supply voltage (VDS = 0.5 V) is applied, the energy band diagram on the source side is higher than on the drain side. In the ON condition, the drain to source voltage (VDS) raises the valance band (VB) just above conduction band (CB) at the source, tunnelling distance narrows, and further tunnelling at the source-channel interface is possible. The electric potential change along the channel of the H-TFET is seen in Fig. 2(b). Source side potential is low, while at the drain, it is high. The power supply and work function of the source and drain metal contacts determine the potential variance through the system. The electric field variations for the Off and ON states is seen in Fig. 2(c). At the source-channel terminal, the electric field is at its peak. For the Off state, the tunnelling width is larger and the depletion width is also larger, resulting in a smaller electric field than in the ON state. The electron Band-To-Band Tunnelling (e-BTBT) together with channel length can be seen in Fig. 2(d). This plot is straight around zero for the OFF-state, indicating that there is no tunnelling occurs, whereas in the ON-state, there is still a significant rise in tunnelling rate near the source channel contact. The figure shows why Ioff is still so low and Ion is really high.
We can get the transfer characteristics by the help of ATLAS Silvaco TCAD tool. The transfer characteristics is shown in Fig. 2(e). The figure illustrates the drain field is current (I DS ) Vs. gate voltage (V GS ) at V DS =0.5 V. When the switch is turned on, the drain current is 1:6ñ10 À4 A/ µm.The tunnelling width is very short and the electric field is very large at the source channel interface, therefore current is higher. The output characteristics of the proposed device is shown in Fig. 2(f). Figure 4 depicts the relationship between drain current (I on ) and V DS . In the log scale, the I on varies in accordance with the drain voltage. The I ON current value is 1:6ñ10 À4 A/µm. TheI on /I off current ratio is in the order of 10 14 .
First we took some default parameters like oxide material, channel length (L C ), channel thickness (w c ), oxide thickness (t ox ). Further we modified parameters to get better results in I on current, I off current and I on /I off ratio.

Effect of Variation of Oxide Material
First we change oxide material and see which material gives best result. We keep other parameters as unchanged like channel length is 25nm, channel thickness is 10nm, and oxide thickness is 2nm for this analysis. In Fig. 3c, we can see how transfer character characteristics changes with the oxide materials. Since oxide materials are dielectric and have different dielectric constants, the current value can change. HfO 2 (k = 25), Al 2 O 3 (k = 8), SiO 2 (k = 3.6). For HfO 2 , we found that the optimal values of I on , I off and I on /I off are3.41ñ10 À06 A/µm, 5.76ñ10 À18 A/µmand5.92ñ10 11 A=μm respectively.

Effect of Variation of Channel Length
After oxide material, we change the channel length from 20nm to 40 nm with 5 nm step and optimized result. For this analysis we take HfO 2 as oxide material and keep other parameters constant w c and t ox as 10nm and 2nm respectively. I d -V gs characteristics graph for different values of channel length (L c ) [17] is shown in Fig.  3(a). By increasing the L c , I off current will decrease for low V gs values from 0.0 to 0.2 V. The overall I on /I off is also increased till L c =30 nm. The highest I on /I off obtained at L c =30 nm shown in Fig. 3(b). For L c =30nm, we obtained optimal value for I on , I off and I on /I off as 3.46 ñ10 À06 A/µm, 7.8 ñ10 À19 A/µm and 4.43 ñ10 12 A=μm respectively.

Effect of Variation of Channel Width
We try to optimize channel width after we got optimized value for channel length L c =30 nm, keep this constant for this analysis. We vary w c from 2 to 6nm and 10 nm. In Fig. 4(a), we can see the transfer characteristics of current for different value of w c . The optimized values at w c =2nm for I on , I off and I on / I off are 6.25ñ10 À05 A/µm, 1.45ñ10 À18 A/µm and 4.28ñ10 13 A =μm respectively.

Effect of Variation of Oxide Thickness
We also check optimize value of oxide thickness (t ox ) after we got optimized value for channel width. We keep all parameters constant for this analysis. We take two values for t ox 1nm and 2nm, and see the variation in drain current in Fig. 4(b), we can see the transfer characteristics of current for different value of t ox . The optimized values at t ox =1nm for I on , I off and I on / I o f f are 1:6ñ10 À4 A/µm,2.1 ñ10 À19 A/µm ,7.6 ñ10 14 respectively.

Effect of Variation of Work Function
We further vary the work function of metal for optimizing the value of I on /I off and SS avg (Subthreshold slope). We found that at work function equal to 4.5 eV, we obtained optimized value for I on /I off and SS avg as 7.6ñ 10 14 and 32.34 mV/dec respectively. The variation of I on /I off ratio and Subthreshold slope (SS avg ) as a function of work function is given in Figs. 4(c) and (d) respectively. Table 2 present a comparison of analog parameters for the various TFET configurations proposed earlier. As we add more improved techniques to get the improved results in our proposed structure, the table shows the increase in I on , I off , I on / I off and SS avg .

RF Parameter Analysis
The parasitic capacitance of the device, including gate capacitance (C gg ), gate-drain capacitance (C gd ), and cutoff frequency (f T ), have been used to assess Frequency response. A rate over which the short circuit current gain achieves unit value is known as the cut-off frequency. This reflects the device's transit time. A connection among f T , C gg , and g m becomes f T = g m /2C gg . C gg is really the gate to gate capacitor, whereas g m seems to be the transconductance. Some visual fluctuations of the suggested TFET's cut-off frequency (f T ) [24] or 3-dBfrequency are shown in Fig. 5. The efficiency for a device at higher frequency being restricted with its cutoff frequency; therefore, the high cut-off frequency will always be desirable. With such a higher cut-off frequency, such device may easily be used for wider band uses. For moreover, its cut-off frequency changes in proportion to the transconductance. Since the improvement in g m overrides the small increase in C gg , our figure showed how f T raises as V GS proceeds. The f T graph, meanwhile, continues to decline once attaining a peak due to a decline in g m as well as an increase in C gg value. In analogue circuit applications, transconductance (g m1 ) is used to relate changes in output current to changes in applied voltage. At constant drain voltage, transconductance (g m1 ) is defined as the rate of change of drain current w.r.t gate to source voltage. The benefit of a higher transconductance value is that the device's amplification gain would be higher [25].

Linear Parameter Analysis
The distortions, and linearity of the system for analogue circuit application are shown by linearity parameters such as HD2, HD3, IIP3, IMD3, VIP2, and VIP3. To see the proper behaviours of proposed device, linearity parameters are very important parameters. The harmonics distortion (HD2, HD3) is high in the transition field, i.e. when switching from ON to OFF. After switchingHD2 and HD3 are decreases with increments in V GS value. Variation of HD2 and HD3 at two drain voltage values i.e. V DS =0.1 and 0.5 V is shown in Fig. 7(a) and (b) .We can see that distortion is more at higher V DS value.
The equation for HD2 and HD3 are given below [26]: Here V i and g m1 are input signal amplitude and transconductance respectively. R S is source resistance.
At a given operating frequency, the voltage intercept point (VIP) reflects the input voltage during which the 1st and 3rd harmonics can have the same amplitude. VIP2 and VIP3 are 2 nd and 3 rd order voltage intercept points respectively. Their expression for calculation are shown below: VIP3 ¼ By the help of VIP3, we can calculate IMD3 (3rd order intermodulation modulation distortion).The amplitude modulation (AM) of a signal with more than one frequency, also known as multi-tone modulation, is defined by IMD3.IMD3 has a value of -14.7561 dBm in our design. By the help of IIP3, we can examine whether the 3rd order harmonics distortions signal amplitude is the same as the reference signal. The IIP3 should have a high value. In our design, IIP3 has a value of-53.8426 dBm at V DS =0.5 V. The expression for IMD3 and IIP3 are shown below [26,27]: The linearity parameters are shown in Fig. 7.

Conclusion
This paper reveals the proposed H-shaped nanotube tunnel field effect transistor (H-NT-TFET) architecture, which has a higher drain current than other TFET architectures. The device's drain current (I on ) is1:6ñ10 À4 A/µm, and its OFF current (I off ) is 2.1ñ10 À19 A/µm, this proposed design exhibit a high I on /I off current ratio, I on /I off =7.6ñ10 14 and threshold voltage V t =0.3449 V at V DS =0.5 V.By the help of linear parameters, we can say that this proposed design is also used in analog application. This device exhibit harmonic distortion parameters HD2 and HD3 values about 6:69ñ10 À3 dBm and 6:8ñ10 À4 dBm respectiely. Other parameters IMD3 and IIP3 having value about − 14.7561 dBm and − 53.8426 dBm respectively at V DS =0.5 V. VIP2 and VIP3 has value of 7.466667 and 1.912366 V respectively at V DS =0.5 V.