Network-on-chip (NoC) is an efficient interconnection designing method for solving the limitations of buses in connecting IP cores. Power consumption is one of the most important issues in this area, solving this problem can lead to a more reliable and efficient design of NoC. Besides, there is another problem which is the More’s law is reaching an end. In this paper, we used a new approach, which improves designing points, so we can design NoC architecture more efficiently based on previous designs. Briefly, this method adds one step before the overall change of architecture which tests if the current design can be improved if we change some internal characteristics. For validation, we applied this method by using wire NoC, and changing its bottlenecks, and make them more efficient by using mapping and adding antennas for wireless communication. While this method seems simple at the first sight, but the result can help many designing, which are vital for industries, and technologies like Wireless Sensor Networks (WSN) and Internet of Things (IoT) devices. Briefly, this method can be used in NoC architectures and make them more efficient in a new style for new purposes. The results compared with the basic designing method with the new improved method; power and Energy improvements are respectively 25% and 46% with mapping and wireless improvements and approximately 60% more than traditional NoC in comparison with the basic method in this approach. This method also paves the way for green computing by avoiding producing more chemicals and products from a reusability perspective.