Device simulation of GeSe homojunction and vdW GeSe/GeTe heterojunction TFETs for high-performance application

Compared with a two-dimensional (2D) homogeneous channel, the introduction of a 2D/2D homojunction or heterojunction is a promising method to improve the performance of a tunnel field-effect transistor (TFET), mainly by controlling the tunneling barrier. We simulate 10-nm-Lg double-gated GeSe homojunction TFETs and van der Waals (vdW) GeSe/GeTe heterojunction TFETs based on a ballistic quasi-static ab initio quantum transport simulation. Two device configurations are considered for both the homojunction and heterojunction TFETs by placing the bilayer (BL) GeSe or vdW GeSe/GeTe heterojunction as the source or drain, while the channel and the remaining drain or source use monolayer (ML) GeSe. The on-state current (Ion) values of the optimal n-type BL GeSe source homojunction TFET and the optimal p-type vdW GeSe/GeTe drain heterojunction TFET are 2320 and 2387 μA μm−1, respectively, which are 50% and 64% larger than Ion of the ML GeSe homogeneous TFET. Notably, the device performance (Ion, intrinsic delay time τ, and power dissipation PDP) of both the optimal n-type GeSe homojunction and p-type vdW GeSe/GeTe heterojunction TFETs meets the requirements of the International Roadmap for Devices and Systems for high-performance devices for the year 2034 (2020 version).

voltage of the basic field-effect transistor (FET) [1][2][3][4]. Compared to a conventional FET, the tunnel FET (TFET) can realize a change by switching with a sub-thermionic steep subthreshold slope (SS) of less than 60 mV/dec due to the avoidance of thermionic charge transport, so that a TFET is more efficient for reducing the supply voltage. However, TFETs have one major bottleneck, i.e., a small on-state current (I on ), and obtaining a sufficiently high I on is a major challenge for TFET applications. Using a two-dimensional (2D) instead of a three-dimensional channel is a possible way to improve the I on of a TFET [5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23], mainly due to the enhanced electrostatic control by the atomic-thin body and the reduced scattering by a surface that is free of dangling bonds. Furthermore, introducing a homojunction or heterojunction architecture [15][16][17][18][19][20][21] in a TFET is a convincing scheme to continuously promote I on compared to a homogeneous 2D channel. Experimentally, 2D TFETs have been fabricated based on transition metal chalcogenides (TMD) and black phosphorene (BP) with good I on and SS [24][25][26][27][28][29][30][31]. Importantly, much higher I on has been observed in BP homojunction TFETs than their homogeneous counterparts both experimentally [29][30][31] and theoretically [18][19][20]. The improved I on by the homojunction arises from the narrower bandgap of a thicker-layer/bulk BP so that the tunneling barrier is narrowed. Monolayer (ML) GeSe is an emerging semiconductor [32] with a puckered honeycomb network like BP. However, in contrast to the instability of BP, ML GeSe has good stability [33,34], which is conducive to the realization of practical device applications. In addition, the medium bandgap [34][35][36][37][38], anisotropic electronic properties [34,38,39], and high carrier mobility [38,40,41] of ML GeSe make it an attractive channel for TFETs [9,11,22]. Also, the bandgap of 2D GeSe is layer-controlled, where a thicker-layer GeSe has a smaller bandgap like that of BP [35]. Apart from layer thickness, a smaller bandgap can also be obtained by a van der Waals (vdW) heterojunction [42]. Given the good characteristics of 2D GeSe and the positive performance of BP homojunction TFETs, excellent performance of GeSe homojunction and heterojunction TFETs is anticipated, specifically when compared to the requirements of the International Roadmap for Devices and Systems (IRDS, 2020 version) [43].
In this work, we study the device performance of doublegated (DG) GeSe homojunction TFETs and vdW GeSe/GeTe heterojunction TFETs with L g = 10 nm using the ab initio quantum transport method. The effect of the homojunction or heterojunction position in a device configuration is first studied. The optimal n-type device is the BL GeSe source homojunction TFET, and the optimal p-type device is the vdW GeSe/GeTe drain heterojunction TFET with optimal I on values of 2320 and 2387 μA μm −1 , respectively, which are 50% and 64% larger than I on of the ML GeSe TFET. Then, we select the optimal devices to further study the device performance limit with V dd . Notably, the device performance (I on , intrinsic delay time τ, and power dissipation PDP) of both the optimal n-type GeSe homojunction and p-type vdW GeSe/GeTe heterojunction TFETs meets IRDS requirements [43] for a high-performance (HP) device for the year 2034 at V dd = 0.5 V.

Models and methods
We construct the ML GeSe, ML GeTe, bilayer (BL) GeSe, and vdW GeSe/GeTe structures (see Fig. 1a-d) and optimize them using density functional theory (DFT) with the Quantum ATK package (2020 version) [44,45]. The Perdew-Burke-Ernzerhof generalized gradient approximation (PBE-GGA) is used to describe the exchange-correlation potential [46]. The vdW interaction between the adjacent layers of BL GeSe and vdW GeSe/GeTe is considered with the Grimme DFT + D2 correction. We select an SG15 norm-conserving pseudopotential with Medium basis set, a density mesh cutoff energy of 100 Ha, and an electron temperature of 300 K. The Monkhorst-Pack k-point sampling is 31 × 31 × 1 [47]. The maximum force and energy convergence criteria are 5 × 10 −3 eV/Å and 10 −5 eV, respectively.
We construct the DG GeSe homojunction TFETs and vdW GeSe/GeTe heterojunction TFETs with L g = 10 nm (see Fig. 2a, b). Two designs are considered for both the homojunction and heterojunction TFETs by placing the BL GeSe or vdW GeSe/GeTe as the source or drain, while the channel and the remaining drain or source use the ML GeSe. In a real device, a 3D electrode as a reservoir is contacted to a 2D channel, and this 3D-2D contact creates a resistance. As this 3D-2D contact resistance is not parasitic-like and cannot be avoided, we estimate the contact resistance by using six-layer GeSe and vdW GeSe/five-layer GeTe electrodes in our computation. The source and drain electrode are pand n-doped with a concentration of 1-5 × 10 13 cm −2 . The device performance is studied with a supply voltage (V dd ) of 0.3-0.74 V, and the IRDS (2020 version) requirements for a HP device [43] with off-state current (I off ) of 0.1 μA μm −1 are used as a standard.
The device performance is investigated by DFT coupled with nonequilibrium Green's function (NEGF) using the ATK package (2020 version) [44,45]. The device simulation k-point mesh for the central region is 31 × 1 × 151, which is the only setting parameter different from the above settings. The transmission coefficient T(E) is acquired by averaging T(E, k x ) over 61 k x -points along the periodic direction, where . The current I (V ds , V g ) is calculated from T (E) with the Landauer-Buttiker equation: [48] Here, G r/a is the retarded/advanced Green's function, �� the line width function with self-energy, f S/D the Fermi-Dirac distribution function, and μ S /μ D the electrochemical potential of the source/drain (S/D).
Note that our calculations are ballistic and quasi-static, so that our results are suitable only for low-frequency conditions and are not appropriate for very high frequencies. The device behavior at high frequency requires the use of a transport model that includes non-quasi-static effects, which is not discussed in this work.
We first determine whether the position of the homojunction or heterojunction, i.e., role as the source or drain, could impact the device performance. The transfer characteristics of the 10-nm-L g GeSe homojunction TFET and vdW GeSe/ GeTe heterojunction TFET are given in Fig. 2. The I on values are extracted from the transfer characteristics at the point V gon = V goff + V dd for an n-type device and V gon = V goff − V dd for a p-type device, and the benchmark I on values for the ML GeSe (this work), ML GeTe [11], ML SnS [9], ML SnSe [9], ML GeS [9], ML WTe 2 [9], ML arsenene [10], ML antimonene [10], ML bismuthene [10], ML BP [9], vertical BP [8] TFETs, and the IRDS HP devices for the year 2022 (2020 version) are given in Table 2. The GeSe homojunction TFET has a higher I on when the BL GeSe is used as the source, while the opposite is the case for the vdW GeSe/ GeTe heterojunction TFET, where a higher I on is obtained when the heterojunction is used as the drain. Also, the I on values of the n-and p-type devices show a discrepancy, and the highest I on values of the n-and p-type devices are 2320 and 2387 μA μm −1 acquired in the BL GeSe source homojunction TFET and the vdW GeSe/GeTe drain heterojunction TFET, respectively, which are 50% and 64% higher than I on of 1548 and 1458 μA μm −1 of the ML GeSe TFET (this work) due to the narrower tunneling barrier that arises from the homojunction and heterojunction, and which outperform the I on of the reported 2D TFETs [8][9][10][11] (101-1667 μA μm −1 ), except for the ML GeTe [11] (2342 μA μm −1 ) and ML BP [7] (2422 μA μm −1 ) TFETs, and the IRDS HP device (912 μA μm −1 ) for the year 2022. The n-type branch of the BL source homojunction TFET and the p-type branch of the vdW GeSe/GeTe drain heterojunction TFET are selected as the optimal devices.
To better understand the improved I on and the discrepancy in n-and p-type branches for the optimal devices, we give the on-state local device density of states (LDDOS) and spectral current of the n-and p-type BL GeSe source homojunction TFET and the vdW GeSe/GeTe drain heterojunction TFET in Fig. 3. For the GeSe homojunction TFET, the narrowest transport tunneling barrier (indicated with short yellow dashed lines in Fig. 3) comes from the BL-ML homojunction for the n-type branch, which is obviously narrower than that of the p-type branch, which comes from the homogeneous ML-ML junction. A similar phenomenon is seen for the vdW GeSe/GeTe heterojunction TFET, where a narrower transport tunneling barrier that comes from the vdW GeSe/GeTe-ML GeSe heterojunction is seen for the p-type branch. As a result, a higher visible peak in the spectral current is seen in the n-type GeSe homojunction and the p-type vdW GeSe/GeTe heterojunction, which explains the higher I on . The narrower tunneling barrier arises from the smaller bandgap of the BL GeSe source and the vdW GeSe/ GeTe drain than the ML GeSe source or drain.
The electrostatic gate control ability is investigated with regard to subthreshold swing (SS) and transconductance (g m ). The SS is defined as the linear relationship of V g to lg I d in the subthreshold region, SS = V g lg I d , while the g m is the The SS of the n-type BL GeSe source homojunction TFETs and the p-type vdW GeSe/GeTe drain heterojunction TFETs is 60 and 58 mV dec −1 , respectively, which is smaller than the SS values of the ML GeTe [11], ML SnSe [9], and ML bismuthene [10]  TFETs and the required 82 mV/dec of the IRDS [43] HP devices for the year 2022 and break/equal the thermal limit of 60 mV/dec of the conventional FETs (see Table 2). Compared to the ML GeSe TFET (this work) with SS of 51-59 mV/dec, the SS of the homojunction and heterojunction devices is slightly inferior, implying an extremely small decline in gate control in the subthreshold area. The g m values are 8.73 and 8.64 mS μm −1 for the optimal n-and p-type homojunction and heterojunction devices, respectively, which are much higher than the g m of 5.38-5.46 mS μm −1 of the ML GeSe TFET (this work), implying much better gate control in the superthreshold area. In combination with the LDDOS, we conclude that the obviously improved I on arises from the enhanced gate control ability in the superthreshold region, in which the narrowed tunneling barrier from the BL GeSe source and vdW GeSe/GeTe drain plays a dominant role. The device dynamic performance metrics, i.e., intrinsic delay time = C g ⋅V dd I on and power dissipation PDP = C g ⋅ V 2 dd , are two other important parameters of transistors. τ represents the switching speed, and PDP represents the energy consumption. In the formula, C g = Qon−Qoff W⋅Vdd is the intrinsic gate capacitance, not including the parasitic capacitance, where Q on/off is the channel charge for the on/off state, and W is the periodic device width. The values of C g , τ, and PDP are 0.086-0.100 fF μm −1 , 0.029-0.058 ps, and 0.042-0.055 fJ μm −1 , respectively, which are quite smaller than the values of 0. 394 fF μm −1 , 0.32 ps, and 0.216 fJ μm −1 of the IRDS [43] HP devices for 2022 (see Table 2). The τ values of the optimal n-and p-type devices are 0.029 and 0.031 ps, respectively, which are much smaller than the most reported 2D TFETs [9][10][11]  The PDP values of optimal n-and p-type devices are 0.049 and 0.055 fJ μm −1 , respectively, which outperform those of the ML antimonene [10], ML arsenene [10], and ML WTe 2 [9] TFETs (0.103-0.17 fJ μm −1 ), and comparable to the other reported 2D TFETs (0.027-0.054 fJ μm −1 ) [7][8][9][10][11], indicating good behavior of the homojunction and heterojunction TFETs in energy consumption. We then study the performance of the optimal n-type GeSe homojunction TFET and optimal p-type vdW GeSe/ GeTe heterojunction TFET under a lower V dd of 0.3-0.65 V, Table 2 The device performance of the BL GeSe homojunction TFETs and vdW GeSe/GeTe heterojunction TFETs for HP application (V dd = 0.74 V) compared with the ML GeSe (this work), ML GeTe [11], ML SnS [9], ML SnSe [9], ML GeS [9], ML WTe 2 [9], ML arsenene [10], ML antimonene [10], ML bismuthene [10], ML BP [7], vertical BP [8] TFETs, and the IRDS [43] HP devices for the year 2022 (2020 version) We take L g = 10 nm, which is smaller than the IRDS required L g of 16 nm. Here, I on = on-state current; SS = subthreshold swing; g m : = transconductance; C g = total channel capacitance, not including the parasitic capacitances; τ = intrinsic delay time; PDP = power dissipation and the transfer characteristics are given in the bottom right panel in Fig. 2a, b, respectively. We benchmark I on , τ, and PDP of the optimal homojunction and heterojunction devices against the ML GeSe TFETs [11] and the IRDS [43] HP devices (2020 version) in Fig. 4 and Table 3. The decreasing I on , growing τ, and decreasing PDP with V d indicate the descend of switching speed and energy consumption simultaneously. Compared to the ML GeSe TFETs [11], I on of the GeSe homojunction TFETs and the vdW GeSe/GeTe heterojunction TFETs has improved for all V dd , yet the improved extent descends with the decreasing V dd . At  Fig. 4 a I on , b τ, and c PDP of the optimal n-type GeSe homojunction TFETs and optimal p-type vdW GeSe/GeTe heterojunction TFETs. The IRDS [43] requirements (2020 edition) for HP applications and those of the ML GeSe TFETs [11] are given for comparison Table 3 The device performance of the optimal n-type GeSe homojunction TFETs and optimal p-type vdW GeSe/GeTe heterojunction TFETs for HP application compared with the ML GeSe TFET [11]  GeSe TFETs [11] (see Table 3), implying a decline of gate control in the subthreshold region. The g m of the GeSe homojunction TFETs and the vdW GeSe/GeTe heterojunction TFETs is 1.29-6.83 and 1.45-5.58 mS μm −1 , larger than those of 1.27-3.99 mS μm −1 of the ML GeSe TFETs [11], implying an enhancement of gate control in the superthreshold area. Experimentally, BP homojunction TFETs have been fabricated with bulk BP as the source electrode and ML or trilayer BP as channel and drain electrode [29][30][31]. As a 3D reservoir usually results in the avoidance of contact resistance that is not parasitic-like in any real device built from 2D materials, in this work, we also consider the effect of 3D electrodes by using six-layer GeSe and vdW GeSe/fivelayer GeTe electrodes in our computation. From the band structures of the bulk GeSe, bulk GeTe, five-layer GeTe, six-layer GeSe, and vdW GeSe/fiveL-GeTe heterojunction given in Figure S1, the six-layer GeSe and five-layer GeTe provide good approximations for bulk GeSe and GeTe. The device performance parameters of the 10-nm-L g sixL GeSe source homojunction TFET and GeSe/fiveL-GeTe drain heterojunction TFET at V dd = 0.5 V are given in Table 3. The use of bulk-like electrodes does not significantly change the gate control ability on the channel, as there is little change in SS, g m , and C g for both devices. However, the I on values decrease from 852-893 μA μm −1 to 605-610 μA μm −1 due to the 3D-2D contact resistance that arises.

Conclusions
The device performance of 10-nm-L g DG GeSe homojunction TFETs and vdW GeSe/GeTe heterojunction TFETs was investigated based on a ballistic quasi-static ab initio quantum transport simulation. The I on values of the n-type BL GeSe source homojunction TFET and the p-type vdW GeSe/GeTe drain heterojunction TFET are 2320 and 2387 μA μm −1 , respectively, which are 50% and 64% larger than the I on of the ML GeSe TFET, showing the advantage of imposing a homojunction or heterojunction in a TFET configuration. Notably, both the optimal n-type GeSe homojunction and p-type vdW GeSe/GeTe heterojunction TFETs meet the requirement for IRDS [43] HP devices for the year 2034 (2020 version) at a low V dd of 0.5 V. Our ballistic quasistatic simulations provide a feasible TFET design at ultrascale under low frequencies. We expect that the excellent performance of the GeSe homojunction and GeSe/GeTe heterojunction TFET could accelerate future relevant experimental study.