Design and Analysis of CNTFET based VLSI Interconnects by Using PVT Variation


 With the quick progress in the area of digital electronics results in miniaturization of semiconductor Industries. In Deep Sub Micron regime, because of leakage current, power consumption is turn out to be a major issue; hence constant efforts are being made by the researchers for investigating the various ways to minimize this. There are various methods available for the same and out of several available methods use of Carbon Nano-tube technology is a promising way to design low power circuits efficiently. Here new techniques are introduced for the reduction of leakage power. Here in this work, comparison of the main performance parameters of Copper on chip nano-interconnect with CNTFET has been done. We have measured the impact of ION and IOFF current by applying Process variation in CU and CNT- Interconnects with the variation of Tubes at 32nm technology and analysed the performance of the digital circuits with scaling of technology. The different kind of simulation outcomes indicates that by applying 10% of deviation from normal value in different device characteristics parameters such as Length of Gate (LTube) of the Tube, Width (WTube) of the Tube, Threshold Voltage (Vth) of the Tube, Thickness (tot) of Tube and Source & Drain Doping concentration with Cu and CNTFET interconnects for NFET and PFET with the variation of tubes from 1 to 16. All the experimental outcomes are achieved by using HSPICE simulator using SPICE model of CU and CNT at27oC temperature by using 32nm Berkley Predictive Technology module.


Introduction
In the past near about 40-45 years back, the fastest chips were able to accommodate less than 10000 transistors only. Example includes MOTOROLA 6800 microprocessor series developed in the middle of 1970 in which the transistor size was near about 6.0 micrometer.
With the continuous scaling of the feature size in present era chips known as Very Large Scale Integration (VLSI), we can integrate more than 10 billion of transistors on a single chip and we are able to achieve feature size less than 15 nm. Power consummation, Area requirement, leakage current and time to the market are some of the issues with the VLSI circuits and people are continuously trying to optimize these parameters through the various technological developments from time to time. As per the prophecy made by the Gordon Moore in the year 1965, number of devices or components on a single silicon chip turn out to be doubles in approximately 18-24 months from the present time [1,4].
Carbon Nano tube (CNT) is having excellent electrical and mechanical properties due to its exceptional band structure. Because of exhibition of its remarkable properties, CNT is popularly used as a major Interconnect material in the present day VLSI circuits. CNT are broadly classified as single-walled (SWCNT) or multi-walled (MWCNT). For single-walled (SWCNT) the devices dimensions are less than 1 nm and MWCNT are prepared by connecting various tubes of CNT in which the device dimension greater than 100 nm are attainable [5,6]. The 3-D structure of CNTFET is shown in Fig.1. In this Manuscript we have measured various performance improvement parameters by using Cu and CNTFET interconnect technology, while applying process variation over device dimension of CNTFET technology is considered. The remaining paper is structured as follows. CNTFET structure is study in section II. In Section III RLC interconnects is studied.
Section IV describes the PVT variation by using Cu and CNTFET based interconnects.
Section V deals with the results and discussion, in this section Average power, Delay, PDP and EDP and PVT variation in LTube, WTube, HTube, TTube etc. is calculated by using Cu and CNTFET interconnects. Lastly, we have presented conclusion in Section VI.

II. CNTFET
Carbon nanotube (CNT) is formed with the help of Hexagonal arrangement of carbon atoms to form benzene ring. The arrangement of benzene to form a graphen sheet and by rolling this graphene sheet CNT is formed. If the diameter is lesser than 1nm it is called single-walled (SWCNT), If multiple tubes or bundles of tubes are arranged with single source and drain terminal is called multi-walled (MWCNT). The outstanding electrical, Mechanical & structural properties of CNTFET technology make one of the most reliable VLSI Interconnect material in current scenario.
The parameters of CNT are understood with the crystal structure of CNTs as shown in the And width of the CNTFET gate ( ) is calculated by equation (2) ≈ Max( , × ℎ) Where Pitch is the distance between Centres of two neighbouring SWCNT under same gate, is minimum gate width and N is the no. of nanotube as shown in Fig.3. high-k dielectric like zirconium oxide (ZrO2) and hafnium oxide (HfO2) that's the gate oxide [12]. Then substrate is fully covered by insulating thick SiO2 layer. A Multiple CNTFET channel is formed by inserting large No of nanotube aligned parallel with width of gate. The distance between centres of adjacent nanotube is called the pitch. In simulation work source and drain of CNT are doped with 0.8% doping level, HfO2 used as gate dielectric thickness with 3nm and bulk dielectric SiO2 thickness with 10µm [10][11][12]. CNT has a property that its energy gap ( ) is inversely proportional to its diameter which allows to alter its band-gap by varying the diameter of CNTs. The threshold voltage ( ) of the CNT-FET can be approximated as half of the CNT band-gap [13,14] as Where = 3.033 the carbon-carbon bond energy and q is the electronic charge and by substituting these constant values, the equations can be simplified into Electrical Characteristics: -It exhibits higher electrical conductivity due to chirality vector arrangement both in metallic or semiconductor properties.
Strength and Elasticity:-Carbon atom form a sheet of graphene which is chemically having strong bonding with neighboring atoms.The elastic model of CNT is higher when press the tip of CNT tube it bands and return to its original place when force is realized.
Thermal Conductivity:-CNTFET has higher conductivity due to bonding of carbon-carbon atom which provides higher strength and stiffness against strains. Due to higher thermal conductivity it is having higher potential in nano-scale molecular electronic and sensing devices. CNT is most promising material for choice today because of its properties of material like light weight, flexibility super electrical properties and its mechanical strength.

III. Interconnects
The term interconnects is the combination of linear and non-linear elements like RLC as shown in Fig.4. For critical design process interconnects modelling is necessary aspects, there are many papers which have been published by using Cu interconnects as shown in Fig.5, here we are going to replace it with CNTFET based interconnects which has a huge potential in term of performance parameters [14,16].

IV. Process Variatiability of FinFET Devices
In this proposed research work we have simulated the geometric variation in Tube's Length (LTube), Width of the Tube (WTube), Height of the Tube (HTube), Thickness of the Tube (Tube), Source/Drain Doping (N) and evaluated variation of fin for calculation of mean and standard deviation of ION and IOFF current by using CNTFET at 32nm technology [4]. PTM-MG model is developed by BSIM-CMG, for scaling multigated devices. Monte Carlo simulation is done for cheeking the variability of the device for ten thousand samples for each parameter. From the simulation results ION and IOFF currents were calculated for 3σ deviation of 10% from the standard values for different parameters like LTube, WTube, HTube, TTube, Small deviations on WFF have high impact on electrical behaviour of CNTFET devices. After calculating the mean (µ) and standard deviation (σ), we normalize the standard deviation by dividing with mean ( µ ⁄ ) for checking the variability of the different device parameters [5,18].

V. Results and Discussion
In Table III, dynamic power is measured by using Cu and CNTFET interconnects over various logic gates in term of performance parameters like Average power, delay, PDP and EDP. In Table IV, Static power is measured over various logic gates with all input vector combination of Cu and CNTFET interconnects with the variation of temperature from 25 o C to 110 o C in order to check the failure rate at higher degree.

VI. Conclusion
An unprecedented approach in Cu and CNTFET interconnects for delay, power dissipation and PDP optimization which results drastically reduction in energy consumption. This article proposes PVT variation on different parameters for high speed and low-power interconnects applications. These P-CNTFETs have high Vth and reduces leakage current during idle state.
Result analysis points out that compared to conventional Cu interconnect, the CNT interconnects paired with CNTFET interconnect designs are more energy efficient. CNT-Interconnect saves dynamic power by 89.96%, reduces propagation delay by 77.5% and leakage power dissipation is reduced by 89%. With the reduction of feature size of the device, lower supply voltage and complex vector set, and also there are several issues with scaling to maintain same electric field with new methodologies of design and new EDA tools that would be capable to deal with the latest fabrication process and variability challenges.