Performance Analysis of Dual Material Junction Accumulation Mode tri gate Junctionless SOI FET: Modeling and Simulation

The paper illustrates the performance of Tri-Gate (TG) Dual Material (DM) SOI (Silicon on Insulator) Junctionless (JL) FET operating in Junction Accumulation Mode (JAM). An analytical model is developed to evaluate its performance. The device is also simulated using Silvaco device simulator. Both the analytical and simulation results are compared and found to match closely. Quasi 3-D modeling approach is adopted here to determine the surface potential of the above device. In this technique, the entire 3-D device is segregated into two 2-D devices with certain physical constraints. These 2-D devices are then analyzed separately to obtain the surface potentials, which are added together using suitable multiplication factors to get the surface potential of the 3-D device. This surface potential is, in turn, used to model the threshold voltage, sub-threshold drain current (Id,sub) and the drain induced barrier lowering (DIBL). The proposed device configuration reduces the IOFF significantly and offers excellent immunity to SCEs. The response of the proposed device is studied for the variations of certain device parameters, such as, thickness of High-K dielectric layer in stack gate, channel doping, and the work-functions as well as lengths of the gate metals. Such study will lead to turn the proposed device immune to short channel effects through proper choice of various parameters.

Other features of JL FET include, high I ON : I OF F ratio [1], minimum thermal budgeting, almost ideal subthreshold swing and better roll-off [1,2]. In spite of having these advantages, JL FET suffers from mobility degradation due to heavily doped channels, and reduction in ONcurrent (I ON ) because of high parasitic resistances [3,4]. To resolve the issue of ON-current reduction, Junction Accumulation Mode (JAM) FET has been introduced [5,6]. The scheme of maintaining heavy doping in the source/drain region, while lowering the channel doping, enhances both the I ON , and I ON : I OF F ratio compared to those in JLFET [7,8]. At the ON-state, high electric field at the channel/drain interface gives rise to the hot-electron effects (HCEs) and gate induced drain leakage (GIDL). Gate engineering using dual material has been established as an effective approach to get rid of the reliability issues caused by HCEs and short channel effects (SCEs) in various FET architectures [9][10][11][12][13]. Reduction of gate oxide thickness leads to the gate direct tunneling [14]. Such gate leakage current that occurs due to tunneling can be suppressed by replacing the conventional gate oxide (SiO 2 ) with dielectric material of high-K value [15]. However, formation of the high-K material layer over Si-film creates a rough Si-Insulator interface, which causes the surface scattering and thereby, mobility degradation of carriers [16]. Formation of dual oxide layer (high-K oxide on top of a thin SiO 2 layer), commonly referred to as Gate stacking [17], offers an effective solution to the problem of mobility degradation [18].
Among various gate structures, Tri-gate (TG) provides excellent gate control in sub-100 nm regime and thus attracts lots of research attention. The trigate (TG) architecture shields SCEs and conducts higher current than the DG-MOSFETs [19][20][21][22][23]. Moreover, the fabrication of both n and p-channel TG MOSFETs has been demonstrated in [24,25], which proves its feasibility in real life applications. Tri-gate devices exhibit high I ON /I OF F ratio and power efficiency, which enbales these devices more power efficient than other FETs (planar or Fin). Reduced surface scattering, subthreshold swing (SS) and drain induced barrier lowering (DIBL) make the tri-gate (TG) JLFETs more suitable for analog and digital applications [9,[26][27][28][29]. Improvement in gate-channel electrostatics gives rise to immunity to SCEs, and consequently, pushes down the device scaling limits [30]. Thus, TG-JLFET architecture that possesses the features of both JLFETs and multi gate FETs deserves special attention to prove its suitability in the short-channel regime. With the increasing demand for high packing density, feature size of the device gets reduced. As a result, the SCEs and parasitic capacitances become stronger [31]. Such parasitic capacitances can be controlled by the Silicon-on-Insulator (SOI) technology [32].
So far various analytical modeling of TG architectures have been reported as indicated by existing literature. Katti et al. in [33] modeled a fully depleted SOI MOSFET considering small geometry by solving the 3D Poisson's equation. 3D model of tri-gate JL nano-wire MOSFET with quantum effects was proposed by Holtij et al. [34]. Auth et al. [35] proposed a quasi-3D model that involves mathematics of reduced complexity without compromising the accuracy of the model. In this model, 3D device was split into two 2D devices to solve the potential function. This technique, applied in tri-gate MOSFET with lightly doped channel, yielded accurate results [36]. Various research works were carried out based on the above quasi-3D model [37,38], which will also be adopted in this communication.
To the best of our knowledge, analytical modeling of DM JL JAM SOI TG JLFET with gate stacking is reported here for the first time. In this paper, the proposed device will be analyzed on the basis of variant device parameters such as, thickness of High-K dielectric layer, channel doping, work-functions and lengths of the gate metals. The proposed JL FET will be modeled based on the quasi-3D modeling technique, in which the 3D potential function will be obtained by the weighted sum approximated approach of surface potentials. Analytical modeling of threshold voltage, subthreshold current and DIBL will also be derived from the approximated surface potential. The proposed device will be simulated by TCAD from Silvaco ATLAS device simulator, in order to validate the model. The performance of the device will be analyzed based on the surface potential, threshold voltage, drain current and DIBL.
The literature is organized in a couple of sections, starting from the introduction, which is followed by the device structure and model description. In the next section, analytical modeling is elaborated. Thereafter, the model validation and simulation setup are briefed, which is followed by the result and discussion section. Finally, the study is concluded by enlightening the major findings of this work.

Device Structure and Model Description
The 3-D view of a DM JL JAM SOI TG JLFET is presented in Fig. 1(a). The top view of the device shows a symmetric double-gate structure [as depicted in Fig. 1(b)] and the side cross-sectional view [presented in Fig. 1(c)], which appears as an asymmetric SOI device. The Si-film is wrapped from three sides with stacked oxide layers (Hf O 2 on top of SiO 2 ) of thickness t Hf o2 and t Sio2 respectively, while the effective oxide thickness (EOT) of t ox is maintained. Two metals with different work functions (φ M1 and φ M2 ) are used to form the gate. Different donor densities are considered here for the channel and source/drain (S/D) regions. S/D are doped with higher doping (N SD ) whereas, the channel is doped with slightly lower dopant density (N C ) of the same type. The channel length, width and thickness (height) are assumed to be oriented along x, y, and z-directions respectively.
Proposed device is analytically modeled, as reported in [35,36] with certain geometrical restrictions imposed on the device architecture. They are: i) thickness of the buried oxide layer (t box ) should be greater than or equal to the channel length (L) to reduce interaction between two side gates [36]; ii) channel length should be at least equal to twice of the width/thickness of the device or more, if not less i.e., L ≥ 2W and L ≥ 2t si [37][38][39]. In the perimeter-weighted sum approach, channel potential [ψ(x, y, z)] at any point can be expressed as a function of ψ(x, y) and ψ(x, z). Here, ψ(x, y) and ψ(x, z) are the potential function of symmetrical double-gate structure and asymmetric SOI device, respectively. These potential functions are obtained from the analytical model by solving 2D Poisson's Equation.

Surface Potential Model
The surface potential of the DM JL JAM SOI TG JLFET is derived by dividing it into symmetrical double-gate and asymmetrical SOI structures as shown in Fig. 1(a), (b). The channel in both the structures is splitted into two sections, based on its overhead metal gate work function. These structures are modeled as follows,

For symmetric DMG-JLFETs
Let, ψ 1 (x, y) and ψ 2 (x, y) be the potential profile for region-1 (with gate work function φ M1 ) and region-2 (with gate work function φ M2 ) respectively. The 2D Poisson's equation for both the regions are given by, Where, q, si and N C represent the electron charge, permittivity of Si-substrate and channel doping concentration respectively. The potentials in the channel are assumed to maintain the parabolic profile [38] and can be represented as, Where, the x dependent coefficients, i.e., can be obtained using the boundary conditions [39] as follows, A) The surface potential at y=0 for region-1 and 2 are given by: B) The electric field at the top of the channel (y=0) for both the regions are given by: C) The electric field at the bottom of the channel (y=W) is given by: D) The surface potential at the source end (x=0) is given by, Where V T is the volt equivalent temperature (=kT /q). E) The surface potential at the boundary of two regions (x = L 1 ) is given by Where V m is the surface potential developed at the boundary of two regions. F) The surface potential at the drain end (x=L) is given by Considering these boundary conditions the generalized channel potential functions are obtained as, And at y=0 the solution of the differential Eqs. 1a, 1b yields, The expressions of λ 1 , K 1 , K 2 , K 3 , K 4 , P 1 and P 2 are given in Appendix.

For Asymmetric SOI-JLFET
Following the previous analytical model of determining the surface potential, the asymmetric SOI-JLFET is also modeled in this section. ψ 1 (x, z), ψ 2 (x, z) be the 2-D potential function of region-1 and 2, which can be obtained by solving the 2D Poisson's Equation as follows, Considering the parabolic potential distribution along the channel region, the potential functions (ψ 1 (x, z), ψ 2 (x, z)) may take the following form, The co-efficients C 11 (x), C 12 (x), C 13 (x), C 21 (x), C 22 (x) and C 23 (x) can be obtained using the boundary conditions ( (3) to (8)) for this asymmetric structure. The potential profiles at z=0 may hold the following form, The expressions of related coefficients are illustrated in Appendix. The generalized potential function at any point in the channel region of the 3D DM JL JAM SOI TG JLFET can be obtained by multiplying ψ i (x, y) and ψ i (x, z) (i = 1, 2, d1, s1) with appropriate factors, as follows,

Expression of V m
The voltage at the interface of two regions (region-1 and region-2) (V m ) is determined in this section. Interface voltage (V m(DMG) ) of symmetric DMG-JLFETs can be obtained by making electric field in Region-1 and electric field in Region-2 equal at x = L 1 (electric field continuity).
The expression of V m(DMG) is Interface voltage (V m(SOI ) ) needs to be measured for the asymmetric SOI-JLFET structure also following the similar approach mentioned above.

Threshold Voltage (V th ) Model:
The threshold voltage is measured as the value of gate voltage (V gs ) at which minimum surface potential reaches to the twice of its bulk Fermi potential [40]. Mathematically, In DMG-JLFET, for region-1, x min = (λ 1 /2) ln K 2 K 1 and for region-2, x min = (λ 1 /2) ln K 4 K 3 . Putting these expressions of x min in Eqs. 10a and 10b yield, can be expressed as, Putting these expressions in Eqs. 19a and 19b yields, The solution of which gives the threshold voltages (V th1 , V th2 ) as follows, Therefore, the threshold voltage (V th,DMG ) of DMG-JLFET is the maximum of the two threshold voltages which may invert the entire surface underneath both the gates, i.e., Similarly, the threshold voltage for the two regions and the entire asymmetric SOI-JLFET structure can be obtained and denoted as V th s1 , V th s2 , and V th,SOI = (V th s1 , V th s2 )| max , respectively.
Thus, the threshold voltage of the DM JL JAM SOI TG JLFET is

Sub-threshold Drain Current (I d ,sub ) Model
Modeling of sub-threshold drain current is obtained from the current density along x-direction [41,42]. The expression is derived taking into account of the drift and the diffusion components of the carriers, as follows, Here, ψ 1 (x), ψ 2 (x) are obtained from Eqs. 14a, 14b.

DIBL
The DIBL is measured as the deterioration of V th [13]. At a specific V ds , DIBL can be obtained by the following expression,

Device Parameters and Simulation
The DM JL JAM SOI TG JLFET is studied for the parameters are given in Table 1. All the simulations are carried out in Silvaco ATLAS device simulator using the standard density models.   [43]. Robust Meshing strategy is adopted for accuracy. The empirical terms introduced in the model are taken from [42,44]. The body (substrate) and the source terminals are shorted and connected to ground. The model data of transfer characteristics is calibrated with the experimental data [45] in Fig. 2. The data obtained from simulation and analytical modeling are plotted and analyzed to examine the performance of the device.

Results and Discussions
In this section, the data obtained from simulation and analytical modeling are plotted and analyzed to examine the performance of the device. Figure 3(a)-(d) shows the surface potential variation along the channel length for different parameters. In Fig. 3(a), the above variation is presented for different high-K oxide thickness. With increase of t Hf O 2 , the EOT increases and associated gate capacitance reduces. As a result the surface potential shifts upward reducing the immunity of the device from SCEs. Figure 3(b) shows the similar variation for two different channel dopings, which are carefully chosen such that the device still works in junction accumulation mode (JAM). As channel doping increases, higher electron concentration in the channel enables the surface potential to move up. This implies that the device with higher channel doping, while working in JAM, is less shielded against SCEs. Figure 3(c) presents the surface potential variation for different ratios of the lengths of gate metals with high and low work function (L 1 : L 2 ). It can be seen that, as the length (L 1 ) of the gate metal of higher work function is reduced with the associated increase in the other gate metal length (L 2 ), the overall surface potential profile shifts upward, and the surface potential minimum shifts towards the source end. Since the upliftment is significant compared to the left shift of the surface potential minima, the device with this configuration of gate metal workfunction is more influenced by drain voltage fluctuation. As the peak electric field shifts more towards the source side and that there is more uniform electric field in the channel. Figure 3(d) presents the potential variation for different work functions of gate metals. Increase in the dual gate metal work functions raises the work function difference between the gate and the substrate, and thus, pushes the surface potential profile downwards. It results in enhancement of the device immunity against SCEs.
Variation of the threshold voltage with the channel length for different values of t Hf o2 , N C , L 1 : L 2 and work functions are depicted in Fig. 4(a) -(d). The smaller t Hf o2 raises the gate oxide capacitance that causes increase of the threshold voltage [in Fig. 4(a)]. Figure 4(b) shows the dependence of threshold voltage on the channel doping. It is observed from the figure that higher the channel doping, lower is the threshold voltage due to the increased channel conductivity. Thus, the leakage currents also increase. Figure 4(c) shows the threshold voltages for different values of L 1 : L 2 ratio. It is quite clear from the plot that lowering the length (L 1 ) of the gate metal of higher work function reduces the threshold voltage. The variation in threshold voltage (V th ) for different gate work functions is depicted in Fig. 4(d). V th rises up with the increase in gate work function. The lower the V th value, the device turns ON earlier. Therefore, with this work-function engineering, the same device can be operated as a low/high-V th transistor, which is an important aspect of low power circuit design. Figure 5(a) -(d) presents the transfer characteristics of the proposed device structure for the above device parameters. The drain current is plotted here in log scale as we are mainly interested in the sub-threshold current (I OF F ). The gate voltage is varied from 0 to 1 V, while the drain voltage is kept fixed at 0.8 V. It is evident from Fig. 5(a) that the OFF-current increases with the increase in high-K oxide thickness. This occurs due to the fact that the threshold voltage reduces with the increment of t Hf O2 as evident from Fig. 4(a). Thus, the device with a thinner high-K oxide (Hf O 2 ) layer improves its immunity to SCEs. It can also be achieved with the reduced channel dopant concentration, as evident from Fig. 5(b). Increase in channel doping enhances both the ON and OFF-current, thereby pushing the device more into the critical zone. Extending length of the gate metal of higher work-function reduces the I OF F , causing improvement in device performance in the short channel regime [in Fig. 5(c)]. Fig. 5(d) indicates that the device with gate metals of higher work functions yields better sub-threshold behavior through reduction in the OFF-current.
The plot of DIBL versus channel length for different t Hf o2 , N C , L 1 : L 2 and gate metal work functions are shown in Fig. 6(a) -(d). It is evident from Fig. 6(a) that the device with short channel (L < 25 nm), the DIBL increases rapidly as channel length reduces, and more so for larger values of t Hf o2 . However, with the increase in channel length (L > 25 nm) DIBL reduces significantly for all t Hf o2 , as it should be. Figure 6(b) clearly shows that lower channel doping forces the DIBL to reduce remarkably. Hence, lower channel doping compared to the source/drain doping makes the device more immune to short channel effects. Figure 6(c) depicts that 2:1 gate length partition yields the lowest DIBL compared to other two partitions. The lowest DIBL is also obtained, as evident from Fig. 6(d), for the reduced gate metal work functions.
In all of the above figures, the analytical and simulation results show close match.

Conclusion
In this work, the performance of a trigate dual material JAM SOI JLFET with gate stack has been studied based on analytical modeling, and numerical simulations. The performance of the proposed device has been investigated by varying high-K oxide layer thickness in gate stack, channel doping, gate metal work functions etc. Significant improvements in combating the SCEs are evident from graphical presentation of the simulation and analytical results. The channel doping lowering from 10 18 cm −3 to 10 16 cm −3 has been found to result in 4% increase in V th , 80% decrease in I OF F and 16% reduction in DIBL. Again, increase in work-functions of both the gate metals by 0.1 eV induces 73% increment in V th , while respectively 45% and 80% reduction in I OF F and DIBL. With reduction in the high-K oxide layer thickness, the surface potential gets lowered, which in turn, increases the threshold voltage and decreases the OFF-current. To be more specific, reduction of t Hf O2 by 2 nm causes at most 6.4% rise in V th and 70% fall in I OF F ; but the DIBL suffers an increase by 7%. Therefore, our present study suggests that proper choice of various device parameters (channel doping, high-K oxide thickness in gate stack) along with the appropriate materials (gate metals) may make the proposed device structure immune to SCEs and thereby, quite efficient while operating in short-channel regime for low power applications.