Ge-Source Based L-Shaped Tunnel Field Effect Transistor for Low Power Switching Application

In this work, the performance of the heterojunction L-Tunnel Field Effect Transistor (LTFET) has been analyzed with different engineering techniques such as bandgap engineering, pocket engineering, work-function engineering, and gate dielectric engineering, respectively. The electrical characteristics of the device has been investigated by using Synopsys Sentaurus TCAD tool and compared with some recent other TFETs. The device has been analyzed in terms of DC as well as AC analysis and offers ON-state current of 2.12*10−5 Aμm−1, OFF-state current of 1.09*10−13 Aμm−1, current ratio of ~108 and sub-threshold slope (SS) of 21 mV/decade and the threshold voltage of 0.26 V and compared to the conventional Si/Ge source L-shaped TFETs without pocket simulation result. The pocket engineering techniques suppress the leakage without degrading the ON current, threshold voltage and SS of the proposed device. The simplified fabrication steps of the proposed device have also been discussed. The proposed L-TFET is free from ambipolarity issues and can be used to develop low-power switching devices.


Introduction
In the rapid advancement of Internet of Things (IoT) and wearable technology, low power operation is a huge concern for digital applications [1]. Though MOS devices can be utilized in microprocessor and static RAM (SRAM) for low power application but the subthreshold swing (SS) cannot be lowered below 60 mV/dec [2]. On the current technology nodes, rapid switching and scaling are the substantial factors as per the device requirements. The downscaling of metal oxide semiconductor field-effect transistors (MOSFETs) dimensions in sub-nanometre region increases the proximity between source and drain increases that further reduces the controlling capability of the gate over the channel. Also, scaling down the MOSFET leads to high SS, short channel effects, and leakage current [3]. The gated reverse-biased p-i-n diode named Tunnel Field-effect transistor (TFET) works on the principle of band-to-band-tunnelling (BTBT) and exhibits low leakage current and reduced short channel effects. It has been appeared as a promising candidate due to its steep slope (SS < 60 mV/dec) and can be used for low power applications [4,5]. However, TFET withstands some limitations like low on-state current, large ambipolar current, and poor RF performance that demand additional improvements [6,7]. These technical issues can be entangled by using different design approaches like using high-k material as dielectric [8], III-V semiconductors [9], low-band gap material [10], and making different shaped TFET [11,12].
Several researchers have reported different strategies to overcome the shortcomings of TFET [12,13]. The on-state current can be increased by increasing the gate-source overlap that enhances the tunneling area, using doped pocket [14], and hetero gate dielectric [15]. Another solution is to increase the effective channel length by structural changes like recessed channel and mesa structure [16]. The ambipolarity can be reduced by considering asymmetric source-drain doping, large band gap materials for drain, gate-drain overlap, and heterogeneous gate dielectric, etc. [17,18] but it is not possible to fully remove the ambipolar current in TFET. Also, these strategies can result in some serious problems in TFETs like increases in drain resistance, lowers on-statecurrent or makes the process more complex [19]. The ultra-low power applications require high on-state current to enhance the fan-out and low off-state/leakage current to reduce the stand-by power consumption. The leakage current depends upon the device design parameters. The moderate body doping suppresses the off-state current and enhances the on-state current. The optimization of device parameters is done ina way to achieve high on-state current, low off-state current, and negligible ambipolar behaviour.
Considering all the above points in mind, in this paper, authors reportedGe-source based L-shaped gate Tunnel Field Effect Transistor (LTFET) with pocket has been reportedand compared with Si based LEFET with and without pocket by using Synopsys TCAD tool. Theproposed device has been optimized in term of various parameters such as source doping, pocket doping, different BTBT models, gate oxide variation, work function variation. This paper is organized as follows. The proposed TFET structure and simulation methodologyare described in section 2. In section 3, homo and heterojunction TFET with and without pocket are explained. Section 4 and 5 deal with the optimization of the proposed device and fabrication process flow respectively. In section 6, DC analysis and AC analysis are presented. Section 7 deals with the comparative analysis of the proposed device with already existing structures. Finally, this paper is concluded.

Proposed TFET Structure and Simulation Methodology
In TFET, the movement of thecarrier depends upon the BTBT phenomena and the tunneling probability depends upon the height, width, shape of the potential barrier, and tunneling mass of charge carriers. Kane's approach and Wentzel-Kramers-Brillouin's approach (WKB) approaches can be used to calculate the rate of BTBT [20]. The rate of tunneling is given in eq. (1) [21]: where q = electron charge, F = average junction field, E ┴ = transverse component of total carrier energy, E = the impact of the transverse-energy-state carriers on the tunneling magnitude. Figure 1 shows the cross-sectional view of proposed LTFET device with Ge as source material and HfO 2 as gate dielectric.  In the source region, the low band gap material Ge offers higher tunneling in the on-state while on the drain side the high band gap material Si lower the tunneling. The Aluminium as metal gate and HfO2 as gate oxide of 4 nm physical thickness has been used. For all simulation, the value of dielectric constant of HfO 2 is 27.The length of source and drain regions are 40 nm each while width of source is 40 nm and drain is 55 nm. The width of pocket and channel regions are 15 nm while length of pocket is 40 nm, respectively. The length and width of gate material is 40 and 50 nmwheras the gate length is 32 nm, respectively. Table 1 shows the TFET device parameters considered for simulation.
In Sentaurus TCAD, all the simulation has been done by using non-local BTBT model. To account the effect of high doping concentration on carrier mobility, Doping Dependent Mobility model has been used. Also, Shockley-Read-Hall (SRH) Recombination Model has been used. The accurate modeling of charge carrier transport in LTFET is achieved by activating, doping density, band gap narrowing, and thermionic models. All the simulations have been carried out at room temperature.

Homoand Hetero Junction TFET with and without Pocket
Considering the device dimensions mentioned in Table 1, the simulation study of LTFET structure using Si and Ge as source region material was performed. The analysis has been carried out for LTFET with pocket and without pocket structures by taking Si and Ge as source materials. It has been observed that LTFET device using Ge as source material exhibits very good performance as it has high on-state current and low leakage current. But in Si based LTFET though the  off-state current is low, the on-state current is also poor. On comparing the results with pocket and without pocket structures, the Ge-LTFET with pocket device shows very good results because of the high I ON /I OFF ratio. Further analysis has been carried out using Ge with pocket structure. The influence of the use of pocket is more noticeable in off-state current than in on-state current. The simulated results of Ge-LTFET and Si-LTFET with pocket and without pocket are plotted in Fig. 2. Ge-LTFET device shows very good performance as there is no ambipolarity observed in the results. All the obtained results I ON , I OFF , I ON /I OFF ratio, SS, g m , V th for both Si and Ge based LTFETs with and without pocket structures are given in Table 2.

Calibration of Proposed Device
First of all, the simulation data of the proposed LTFET structure is calibrated against the experimental data of reference [22] at drain voltage 0.5 V as shown in Fig. 3. It is observed that there is a good matching of both data, which certifies the validity of the selected models. The optimization of the proposed LTFET has been done by changing different parameters like using the different band to band models, variation in source and pocket doping concentration, gate oxide variation, work function variation and the transfer characteristics, I ON /I OFF ratio, SS, and threshold voltage of the device are obtained.

Different Band to Band Models
BTBT can be achieved by two processes; the first is direct tunneling and the other one phonon-assisted tunneling. In direct tunneling, there are two models, local and non-local [23]. In Sentaurus TCAD, various local BTBT tunneling models are Hurkx BTBT model, Schenk BTBT model, Simple (E1, E2, E1_5) BTBT model. The non-local model is named as Non-local BTBT model. In both local and non-local models, the electron-holes generation profiles are different. In the former case, electron-holes generation profiles are the same while in the latter case holes are generated at the beginning, and electrons are generated at the end of tunneling.
In TCAD tool, for Schenk BTBT model bandgap narrowing model can be used in two ways. Simply, bandgap narrowing can be computed without depending on temperature (at T = 0 K) and in the other way, temperature dependence is accounted. In Hurkx model, tunneling carriers are modelled by an additional generation-recombination process. The Hurkx model can be written as eq. 2 [24]: where R BTBT is the BTBT rate, and the coefficients A, B, D,andp can be specified in the BTBT parameter set. These coefficient values can be used to define carrier generation and recombination. E1, E2, E1_5 selects the simple models. The Non-local BTBT model implements the nonlocal generation of electrons and holes that occurs because of the direct and phonon-assisted BTBT processes. In the direct bandgap semiconductors, direct tunneling occurs. But in the indirect semiconductors (Si and Ge), the phonon-assisted tunneling process dominates. The electron-holes generation rate is obtained by nonlocal path integration. Suppose atunneling path of length l is given that starts at x = 0 and ends at x = l. The holes are generated at x = 0 and electrons are generated at x = l. The net hole recombination rate due to phonon-assisted tunneling can be written as eq. 3 [25]: where h is the Planck's constant, g is the degeneracy factor, ρ is the mass density, κ V and κ C are the magnitude of imaginary vectors. D op , ε op and N op are the deformation potential, energy, and the number of optical phonons, respectively. Figure 4 shows the simulation results of proposed LTFET using different models. Both local and non-local were used one by one and results were obtained. In non-local models, different tunneling paths are considered. For every different tunneling path, the electric field at each point of the path changes dynamically. Using non-local model, the change in theelectric field at each point of every tunneling path is determined and hence more accurate results are obtained. Also, from the results, it is very evident that non-local BTBT model gives the best results among all the models.

Source & Pocket Doping Variation
The effect of changing the doping concentration in source region and pocket region has been discussed here. For both cases, three different concentration values were considered.
As shown in Fig. 5a, for source doping region, the concentration values 1E17, 1E18, and 2E18 were taken for simulations. From the obtained results it has been found that the source concentration 1E18 can be considered for further analysis as it shows high onstate current and low off-state current. Figure 5b shows the obtained results for variation in pocket doping concentration. In this analysis, the concentration values 1E18, 1E19, and 2E18 were considered for simulations. It is evident from the results that pocket doping with concentration value 1E18 shows low off-state current and high on-state current. For further analysis, the source and pocket doping concentration values are fixed i.e.1E18.

Gate Oxide Variation
The gate dielectric should be chosen carefully to achieve high on-state current and low SS. In this analysis of LTFET, the It is very clear from Fig. 6 that thehigh dielectric constant material HfO 2 shows superior performance over the other two materials (SiO 2 and Si 3 N 4 ). On increasing the dielectric constant, the on-state current increases. The small dielectric thickness offers the solution to the problem of low on-state current.

Work Function Variation
In LTFET, the variation in the work function of gate metal was done to observe the effect on drain current. The work function values were varied from 4.3 eV to 4.7 eV. Figure 7 shows the simulated results of drain current vs gate voltage at different work functions. Increasing the work function reduces the on-state current.
For the work function value of 4.3 eV, the LTFET exhibits high on-state current and low off-state current. The variation in work function causes the variation in threshold voltage, onstate current, and off-state current. The simulated value of threshold voltage of 0.58 V was achieved for ϕ m = 4.3 eV and 0.87 V was obtained for ϕ m = 4.7 eV.

Fabrication Details of the Proposed Device
The proposed LTFET can be fabricated by using CMOS compatible process flow as shown in Fig. 8. Following steps have been required for the possible fabrication of the proposed device. Firstly, intrinsic silicon layer is deposited over SiO 2 (Fig.  8a).
Thermal Oxidation and Diffusion Thermal oxidation is used to grow the oxide layer for passivation of i-channel region. Diffusion method is used to dope the silicon layer (n + layer) for the formation of pocket and drain regions (Fig. 8b). The drive-in process is followed by diffusion process. In this process, the dopants are forced to drive inside the doping windows of the wafer as a result surface concentration decreases and dopants move further. Etching: The etching of Si can be done by using dry etching method or wet etching method. In dry etching, gas plasma etches Si (isotropic/anisotropic) depending upon the gas recipes used. In wet etching method, chemicals are used to etch Si. After patterning the oxide, etching of Si layer is done (Fig. 8c and d).
Low Pressure Chemical Vapour Deposition (LPCVD) LPCVD method has been used to deposit a 40 nm thick Ge layer to form the source region. Further the Ge layer is p + doped by using diffusion method (Fig. 8e).
Atomic Layer Deposition This technique has been used to deposit HfO 2 as gate oxide (Fig. 8f).
Sputtering This method is used to deposit thin films of various materials. Aluminum gate can be formed using sputtering method (Fig. 8g). At last the spacer layer, Si 3 N 4 can be deposited using LPCVD/ Plasma Enhanced Chemical Vapour Deposition (PECVD) method.

Results and Discussion
The simulated results of LTFET device have been presented in this section. The source and back gate is kept at ground potential. The different device analysis like DC analysis, AC analysis and the effect of different parameters on the device performance are presented in subsections.

Energy Band Diagram
The electrostatic potential distribution of simulated LTFET using optimised device dimensions is presented in Fig. 9a. Figure 9b depicts the energy band diagram of Si and Ge LTFET with pocket structures.
In the proposed device, when the gate overlaps the source, line tunneling occurs and such a TFET structure is also known as line TFET [26]. In this case, increasing the V gs bends the energy band towards the gate oxide until the conduction band edge crosses the valence band edge and BTBT happens. The uniform electric field beneath the gate oxide implies that in line tunneling the effect of V d on the source can be ignored. Below the gate-source overlap, all tunnel paths are available at the same amount of band bending but the paths get shorten as V gs is increased. As the tunneling is located near the gate region and both electric field and tunnel path are aligned, a small amount of V gs is sufficient for band bending. When the TFET is conducting, the stronger the band bending makes shorter the tunnel path. In short, I ON depends upon the overlapping between gate and source. From the energy band diagram plotted in Fig. 9b, it is observed the using Ge as source material in LTFET shortens the tunneling path and more tunneling occurs as compared to Si-LTFET.

Input and Output Characteristics
The transfer characteristic of proposed LTFET is shown in Fig. 10a. The V gs was varied from −0.2 V to 1.2 V for various values of drain voltages. It is evident from the results that the proposed LTFET works very efficiently for the wide range of applied gate voltages. As applied V gs is increased, tunneling current increases. When the applied V gs is equal to V dd, the transistor is in on-state and the corresponding current value is I ON . The I ON of 4.4 μA, 2.12*10 −5 A, 4.32 *10 −5 A and I OFF of 1.03 *10 −13 A was observed for V ds 0.3 V, 0.5 V, 0.7 V. The proposed LTFET structure works very efficiently with high on-state current, low off-state current and no ambipolar behaviour has been observed. The output characteristics of proposed LTFET for the drain voltages range from 0 to 2.4 V for different gate voltages are shown in Fig. 10b. For small values of V ds , BTBT is inefficient because of low carrier density but BTBT rises as V ds is increased. The drain current increases as the V ds is increased until the edge of conduction band in drain region falls below the edge of the conduction band in the channel. After that drain current saturates and V ds has no longer affect the tunneling. On increasing the gate voltage, the exponential rise in drain current demonstrates better gate control. The flat saturation region indicates that the effects like kink effects are highly suppressed in this proposed LTFET. Figure 11 shows the influence of changing the V ds on threshold voltage, SS, and g m . Figure 11a shows that as V ds is increased, the threshold voltage obtained by the constant current method remains the same whereas the threshold voltage obtained by the transconductance method, increases. Figure 11b depicts that

AC Analysis
To determine the AC performance, it is very important to determine the capacitance of the device. Capacitance creates a path between the input and output that leads to circuit oscillations and signal distortion. The change in total gate capacitance (C gg ), gate-drain capacitance (C gd ), and gate-source capacitance (C gs ) with variation in gate-source voltage is plotted in Fig. 12. The increase in V gs increases both C gg and C gd whereas C gs decreases. The capacitances C gg and C gd are accounted when charge carriers are injected from drain to gate. On increasing the gate voltage, an inversion layer is formed that decreases the potential barrier at the drain terminal. Hence, capacitance is increased [27].
The analyzed current driving capability or amplification of LTFET at different V gs is shown in Fig. 13. The reciprocal of output resistance is known as g ds . For high amplification ability of the device, g ds should be low [28,29]. The g m and g ds can be expressed by (5) and (6): g m depends upon the slope of transfer characteristics that determine the switching speed of the device. For high switching speed, a high value of g m is required. As the applied gate voltage is increased, the drain current increases and g m also increases, as shown in Fig. 13a. The output conductance as a function of V ds is also shown in Fig. 13b. For saturation-like region, when V gs is increased, due to BTBT drain current increases and as a result g ds. The ratio of g m /g d is known as intrinsic gain or maximum voltage gain (A v ) as given in eq. (7) [29].
Figure 13c depicts that the intrinsic gain of proposed device remains the same for low gate voltage but then abruptly increases for high gate voltages.
Equation (8) states that f T is directly proportional to g m and inversely proportional to the total gate capacitance. At low voltage values, g m dominates but on increasing the voltage values, total gate capacitance starts dominating. So, the f T starts decreasing once it attains maximum peak as shown in Fig. 14a.
The mathematical expression for GBP is given in eq. (9) that shows GBP depends upon g m and C gd [30]. For the proposed LTFET, Fig. 14b shows the results obtained for GBP with variation in V gs . GBP firstly attains a maximum value as the voltage is increased and then decreases.
7 Comparison with Other LFETs The comparison of the proposed LTFET device with already reported TFET devices like Si TFET, fullydepleted (FD) SOI-TFET with Ge source, Si LTFET, TFET using III-V, etc. is given in Table 3. From the comparison, it can be concluded that the proposed LTFET using Ge as source region is performing very efficiently and further RF noiseanalysis can be done to observe the performance.

Conclusion
Ge-source based LTFET with and without pockethas been investigated and compared with Si based LEFET with and without pocket by using Synopsys TCAD tool. The proposed device has been optimized in term of various parameters source doping, pocket doping, different BTBT models, gate oxide variation, work function variation. The device offers high on-current of 2.12*10 −5 Aμm −1 , off-current of 1.09*10 −13 Aμm −1 , current ratio of~10 8 and SS of 24 mV/ decade and V th of 0.26 V. The investigation shows that proposed device is free from ambipolarity and drain voltage variation does not much effect SS and OFF current. Furthermore, the AC analysis of the device has also been studied found that the proposed LTFET device is a low power device and it is suitable candidate for low power digital applications. Moreover, in the current scenario of an information-based society, it can be used for Internet of Things (IoT) application.