Nonlinearity Analysis of Quantum Capacitance and its Effect on Nano-Graphene Field Effect Transistor Characteristics

A simple, compact, and fundamental physics-based quasi-analytical model for single-layer graphene field effect transistors (GFETs) with large-area graphene is presented using a quantum mechanical density gradient method-based calculation. The device statistical physics of the two-dimensional (2D) graphene channel is studied analytically. This modelling leads to the precise drain current of the GFETs. The drain current calculation for the GFETs starts from charge carrier concentration, its density of states, and quantum capacitance (QC). QC depends primarily on the channel voltage, and is also a function of the gate-to-source voltage Vgs and drain-to-source voltage Vds. The formulation of the drain current with velocity saturation was carried out using the Monte Carlo simulation method. The performance of the analytical GFET model is characterized by the precise values of QC, its impact on drain current, and output characteristics. The impact of QC on FET devices at nanoscale is that it adds nonlinearity to the characteristic curves. The proposed method provides better QC results than the available analytical and simulated models.


Introduction
The heart of electronic devices is the ability of a particular material to control its electronic properties in the presence of another electric field. The ability of the semiconductor industry to determine the electronic properties in the material for electronic devices [1][2][3][4] is also needed in this advanced era. The semiconductor industry, which is already out of scaling limits for siliconbased devices, needs to find the next excellent silicon alternative as graphene. Graphene, after its first physically stable noble experimentation in 2004, is promising to be the next alternative to silicon. Graphene is a single atomic (carbon) thin or thick layer (~3.34 × 10 −10 m), so it is a two-dimensional (2D) material, [5][6][7][8][9] along with high charge carrier mobility 5 of value more than 10 5 cm 2 /V-sec and even thermodynamically stable. The chemical vapour deposition (CVD)-grown graphene layer and graphene growth over a base other than silicon could be a possible option for high-frequency and analog electronic devices and circuits. 8,9 The first physical demonstration of the field emission effect in graphene layers was an experimental device in 2007. The first physical demonstration of the field emission effect in graphene layers was an experimental device in 2007. 5 Due to the rapidly changing world and the technological advancements in recent years, graphene field effect transistor (GFET) models with intrinsic transit frequency and maximum frequency of GFET operation are comparable to or higher than similar sized complementary metal-oxide-semiconductor (CMOS) nanometre technology. [10][11][12][13][14] The current saturation effect in single-layer 15 and bilayer graphene, 16 with high transconductance and transistor resistance values directly affects the GFET performance. The gate/channel length of graphene influences the operating frequency of the proposed GFET model, the high resistance and transconductance values, and graphene RF circuits find their application in defence in real life, so this is the main focus of this particular work. Compact and fundamental physics-based quasianalytical modelling for (GFETs) with large-area graphene is also reported in the literature. 17 Physics-based GFET modelling explores the drain current, capacitance, and charge parameters for the graphene channel. [18][19][20] An explicit compact model of drain current 18 was extended by Jiménez 19 to explore the AC and transient behaviour of the GFETs. Both of these physical frameworks are drift-diffusion charge carrier transport mechanisms. The implementation of the Ward-Dutton charge partition scheme to model the source-drain charges together for transconductance and self-capacitance calculations was reported by Gennady et al. 20 This compact model is benchmark-characterized with measured current-voltage accuracy for prototype devices and predictive behaviour. 21 Also, a few simple mathematical models have provided closed-form formulas for graphene field effect transistor physical parameters, such as g m , r 0 , C gs , and C gd . Many other comprehensive, compact, and analytical models of GFET gate capacitance and quantum capacitance as dependent modelling parameters have already been reported in the literature. However, they all either are limited to modelling and simulation of GFET characteristics, such as some of the most recent GFET models, [22][23][24] or are complex or are practically unfeasible, i.e. not up to date regarding the nonlinearity of GFETs, [25][26][27] with no future application in devices and circuits. The latest GFET model for nonlinearity of ballistic GFETs was presented by MUNINDRA and Nand. 28 The proposed model keeps its nature lucid to present fundamental mathematics, presents the explicit quantum capacitance drives the drain current formulation using it, and the nonlinearity of the characteristic curves of the GFETs at nanoscale. Since noise is always a key element that can disturb the performance of FETs and GFETs in realworld electronic devices and circuits, the study of nonlinearity in the transfer and output characteristics is our contribution to the modelling and simulation of the GFETs. A dual-gate-controlled nonlinearity study presents the transfer characteristic curves in the result and discussion section. Dual-gate control to large-area graphene GFETs is also a new concept for the proposed GFET modelling at 300 nm technology. This paper is organized into four sections (introduction, analytical model, results and discussion, and conclusion). The first section introduces the GFET and presents the diverse available literature, with a detailed explanation of the physics-based GFET model starting from charge carrier concentration and density of states in the second section. This section also explains quantum capacitance, which leads to the drain current formulation helping to plot the graphical results for the GFET at 1000 nm and 300 nm channel length. Section III discusses and compares the experimental results with the proposed model results, and section IV concludes the paper.

Device Structure of GFETs
The proposed compact model of a well-established dual-gate MOS structure in Fig. 1 is a 2D cross-sectional view of the proposed GFETs. The dual-gate metal-oxide-semiconductor field effect transistor (MOSFET) consists of two gates (top and back gate), a large-area graphene sheet as a channel placed on the thick SiO2 back gate oxide layer (300 nm and 1000 nm), where a heavily doped silicon wafer acts as a back gate. This article emphasizes p-type GFETs, while a similar approach applies to the n-type GFETs. The C gs and C gd are the gate-to-source and gate-to-drain capacitance. R ds , R d and R s are the drain-to-source resistance, drain resistance, and source resistance shown in Fig. 2a. This paper produces a fundamental physical model of GFETs for largearea graphene (1000 nm length, 0.342 thick and 1000 nm width (which can be taken even as a few micrometres). V(x) is shown above in Fig. 2b as channel voltage, which is variable and depends on the value of x from 0(0) to L ( V Ds ), where C t , C b and C q are top gate capacitance, back gate capacitance and quantum capacitance, and V gst and V gsb are applied internal voltage. V ds and V BG are the externally biasing drain-to-source and back gate voltage. The small signal equivalent circuit of the proposed GFETs is also shown in Fig. 2c, where R s , R d and R g are the source, drain and gate resistance, respectively.

Formulation of Sheet Charge Carrier Density ( ) and Quantum Capacitance Calculation ( )
The 2D energy and wave vector relation for the mobile π electrons in graphene can be formulated 29 as E(k) = sℏv f |k| where s is equal to +1 in the conduction band and s is equal to −1 in the valance band for the first Brillouin zone (BZ) in graphene layers. Where ( ℏ ) is the reduced form of Planck's constant and Fermi velocity v f is of high magnitude equal to 1x 10 8 cm/s along with |k| , a 2D x-y plane wave vector at the origin |k| = 0 is referred to as the "Dirac point". Each Dirac point has double spin degeneracy g s = 2 and contains double valley g v = 2; thus the number of states in a graphene layer is

3
Here, A is an area of the particular layer, since the linear charge density of states 26 for an intrinsic graphene layer is a differential form of the number of the state of the particular layer with respect to the energy of the particular states, which can be expressed as Thus, the charge carrier (hole) concentration in 2D graphene sheets based on fundamental physics can be formulated as After replacing f(E) as the Fermi-Dirac distribution function and gr (E) as well, the number of holes in the graphene sheet can be written as follows, where Ecv works as reference energy (i.e. it will be taken as Ecv = 0) Similarly, the number of electrons in the graphene channel with respect to field-dependent charge carriers can be expressed as Thus, the total charge (Q net ) is equal to (p − n) and can be utilized to estimate the total sheet charge density Q gr , which is equal to q* (p − n) as follows The quantum capacitance of the proposed device is C q , which can be calculated 26 as the differential of the channel sheet charge density Q gr with respect to V gr , where V gr is the graphene channel voltage where the minus sign here reflects the impact of progressively positive voltage applied to the gate which directly increases the positive channel voltage; i.e. more negative charge results in the graphene layer.
To solve the integral term in the above equation, we take out the constants and substitute the exponential term exp x dx to obtain a simplified equation as follows: A simplified quantum capacitance formulated above in Eq. 9 can be rewritten as by dividing the integral into two parts, partA ′ and PartB ′ as where A is exp (E F /K B T + 1) and B is exp (−(E F /K B T + 1)). Thus, after putting limits in exponential terms and replacing x = 0 and by solving Eqs. 11 and 12 by the two-part integral substitution method, we obtain a combined solution for both partA ′ and partB ′ which further depends on the positive and negative sign as given in Eq. 13, where K B Tlnx ± E F as part I and 1 x * Now, assuming E F as constant, since E F = q.V ch , and by following standard mathematical rules to solve this integral and after applying limits, we obtain the solved part as given below Similarly, after solving part II, Now, by summing up partA ′ and PartB ′ , we can represent a solved integral in quantum capacitance as follows By substituting the values of A and B, and after performing some basic algebraic mathematics, the quantum capacitance can be represented in a simple formula as given below By applying Euler's equation for the trigonometric function to the above exponential terms and by replacing the hyperbolic trigonometric formulas, the quantum capacitance can be presented as By using reverse engineering, we can write the quantum capacitance 29 in even more simplified form as given in log term For the qV gr ≫ K B T condition, Eq. 19 will be simplified to the following single-term formula As the total charge density in Eq. 6 was used to accurately formulate quantum capacitance, channel voltage V gr and quantum capacitance C q have useful significance to formulate gr , so that by using the basic mathematics technique of two equations and two variables, drain current can be formulated using gr .
where the channel voltage V gr can be directly calculated using the basic Kirchhoff voltage law (KVL) and Kirchhoff current law (KCL) technique for the given Fig. 2c and can be expressed as The pre-factor of 1 2 with C q is because of its dependence on V gr , and now by substituting Eq. 23 into Eq. 22, we obtain a simple second-order algebraic equation.
Thus, by rearranging the equation, we obtain a quadratic equation of C q in terms of V gst ,V gsb and V(x), where V(x) is the channel voltage depending on x (0 to L) and the value of V(x) at (x = 0) is 0V, while that at (x = L) is V ds V.

Drain Current Calculation
For drain current calculation, we first need to focus on the charge carrier velocity v = v(x) mainly through the channel (x =0 to L) from (1). A low saturation velocity characteristic as shown by Monte Carlo simulation 30 at steady state is where E represents the electric field, µ is the carrier mobility, and v sat is the saturation velocity at low field. The carrier velocity, in particular v sat , of the graphene channel at the SiO 2 platform is strongly affected by the rare interfacial scattering of phonons. Experimental work has discussed the two dominant optical phonons at the SiO 2 and graphene interface. They showed a magnitude of 59 meV and 155 meV, respectively, but one can describe this phenomenon by a single phonon with enough accuracy and the energy of ℏΩ. By the approach used 31 to calculate v sat , v sat depends on sheet charge carrier density ( s ) and the phonon effective energy Ω.
The charge carrier interaction phenomenon in the graphene-MOSFET channel introduces a new term, 0.5 + A.V 2 (x), 30 to correct the calculation of v sat to one decimal point at the channel drain end. Now Eq. 26 becomes where A is a dimensionless important factor of order 10 −3 , when s is of magnitude 10 12 cm −2 and the final unit will be cm/s. Now, using E = − dV dx and Eq. 20, the drain current ( I d ) becomes (24) after integrating the left side 0 to x and 0 V to V ds V right side, since V = V(x) , is a function of the channel length and by changing the variable of separation I d becomes. Because the pristine graphene layer and GFET graphene channel are two different forms of material, graphene as channel deals with scattering and inhomogeneity of the electrostatic potential. Two pivotal elements must be counted in the drain current: the first is the effect of the inhomogeneity of the electrostatic potential, 32,33 and the second is the interface trap states that will contribute to the DOS of large-area graphene, which also cause scattering nonlinearity characteristics. 22,23 Thus, an extra term in the numerator will be added as puddles

Results and Discussion
To investigate the quantum capacitance effect on gate capacitance, a basic MOS structure without the back gate of oxide thickness (300 nm) and top gate oxide of the thickness (3 nm), zero voltage as V gst ,V gsb and V ds for the proposed GFET model is analysed. Quantum capacitance of the single-layer GFETs presented in this analytical model enhanced and altered the overall gate capacitance concerning the relation C q = C ox * C q ∕ C q + C ox .
One of the most significant aspects of nanoscale GFETs is that quantum capacitance plays a pivotal role in device characterization. Figure 3 shows graphically how the quantum capacitance influences the total gate capacitance at 300 nm and 1000 nm channel length. The proposed model provides better numerical values of Cq (1.5 µf/cm 2 for the presented model results and experimental results, which in comparison with other GFET structures is much higher, as shown in the graph in Fig. 3d at the 1000 nm channel length. The insight investigation of the proposed model capacitances (top gate (29) and quantum capacitance) at different top gate oxide thicknesses is shown in Fig. 3. The numerical value and impact of quantum capacitance increase with a decrease in the top gate oxide thickness (ranging from 30 nm to 3 nm). The comparison of quantum capacitance of the proposed model with the experimental results at 1000 nm, H (56 meV), and with the monolayer graphene H (55 meV) is shown in Fig. 3d. Thus, the simulated results (line) and analytical results (symbol) are comparable to those in the available literature. Table I presents the numerical values for all significant parameters and dimensions of the GFET model. Figures 4 and 5 graphically present the transfer characteristics and output characteristics of the proposed GFET model. The proposed model is compared with the experimental work 15 listed as GFET1 in Table I. GFET1 features a high dielectric 2D gate material HfO2 on exfoliated  The nonlinearity characteristic behaviour of the GFET at 1000 nm and 300 nm channel length is the negative drain current versus the drain current in Figs. 5 and 6. The Diracpoint shift is shown in Fig. 4 after applying an external gateto-source voltage for single-layer graphene, while for the conventional MOSFET Dirac point has the same contact point of conduction and valance band. This Dirac-point shift in transfer characteristics and kink, presented in the output characteristics, is proof of the nonlinear behaviour of the GFETs. This nonlinear behaviour increases when the channel length of the GFETs is decreased from 1000 nm to 100 nm, and the decrease in the channel length shows more kinks. 28 The dual-gate control is graphically presented in Fig. 6. The nonlinear behaviour of the GFETs is observed in Fig 6a and b. Here we concentrate on the nonlinearity of the transfer characteristics of the proposed model. The very slow and gradual increase in drain current at very low gate voltages applied to both gates shows some nonlinearity in transfer curves since it is not conical shaped like the others in Fig. 6a (for −0.1 to 0.1V gate-to-source voltage). An increase in the gate voltage shows a gradual increase in drain current beyond this, which is conventionally and fundamentally formal as in MOSFETs, while in the conventional trend in electronic device characteristic curves, a flat drain current (slow increase) shows nonlinearity in the transfer characteristic curve and is proof of kinks.

Conclusion
A quasi-analytical model for single-layer GFETs with largearea graphene is used to formulate the drain current with velocity saturation effect, and the role of quantum capacitance over the total capacitance is explained with the precise output and transfer characteristics of the proposed GFET model, which is facilitated by a simple mathematical GFET model. The effect of enhanced quantum capacitance at nanoscale adds nonlinearity to the transfer and output drain  characteristics of the proposed GFET model. Thus, the modelling and simulation of the GFETs is presented and the results compared with well-established experimental work. This model will help the reader understand the basic physics of the GFETs. drain current vs drain-to-source voltage for the GFET model. This graph presents top gate control by Vds and back gate control by VBG over drain current (while for this dual-gate control, an exception is considered that the graphene sheet is not a large-area sheet). V ds and V BG are the externally applied drain-to-source and back gate voltage.