Performance Evaluation of Junctionless FinFET using Spacer Engineering at 15 nm Gate Length

In this proposed work, performance of junctionless transistor with the use of spacers has been evaluated at 15 nm gate length in Cogenda TCAD tool. This work is implemented as variation in four parts: changing the spacer extension length, placement of spacers having dual-κ, proportion of low and high-κ spacers, and value of high-κ dielectric constant. Impact of all these parameters is considered on the output of proposed device in terms of various output parameters like on-current (ION), off-current (IOFF), subthreshold swing (SS), drain-induced barrier lowering (DIBL), transconductance (gm), transconductance generation factor (TGF), output conductance (gd), early voltage (Vea) and intrinsic gain (Av). From the simulations, it has been observed that placing spacers of dual-κ along the left and right sides of gate region has improved device performance in terms of output parameters. Due to increased gate capacitances, the increase in dielectric constant value has degraded the device performance for longer spacer extension length. However, for shorter spacer extension length, the device characteristics are improved as the value of dielectric constant is increased. Therefore a trade-off is required to get the optimum results of the device.


Introduction
CMOS technology has grown tremendously over the past few years. The process of Scaling allows more numbers of components to be accommodated over the given chip area. This growth in number of transistor over an IC was well predicted by Gordon E. Moore in 1965 [1]. Below 20 nm technology, it is difficult to form sharp source and drain junctions in planar MOS transistor. For creating these junctions, doping concentration gradient needs to be high and should be processed at low temperatures. Different structures like Fin shaped FET (FinFET) and Double-gate MOSFET (DG-FET) provide superior immunity against adverse effects occurring at short channel, commonly known as SCEs [2]. More than one gate allows better gate control and lowers drain-induced barrier lowering (DIBL) [3]. Junctionless transistor (JLT) was invented by researchers to avoid formation of sharp junctions and cost annealing problems [4]. This kind of structure doesn't have any junctions between source-channeldrain regions. All these regions have same doping type and concentrations. The JLT can act like a resistor where gate voltage controls the drive current [5]. JLT has advantages of being simple from fabrication point of view and requires low thermal budget [6]. Compared to inversionmode (IM) FETs, junctionless (JL) FET has more reliability which was demonstrated by Toledano-Luque et al. [7]. Junctionless accumulation mode (JAM) FinFET based on Bulk isolated junctions was demonstrated in 2013 for the first time [8]. This structure has lower cost of substrate than Silicon on insulator (SOI) and was compatible with existing CMOS technology.
The effect of high-κ material as spacer in Junctionless transistor was investigated which showed the improvement in device performance and has lesser short channel effects [9]. Dual-κ spacers are combination of low and high-κ materials acting as spacers. High dielectric spacers are generally used nearer the fin, which lowers the leakage current and hence lesser SCE due to increased fringe field coupling between gate and region of underlapping [10].
Dual-κ spacer impact was demonstrated on double gate FET that controls the direct tunneling between source and drain [11]. Dual-κ spacer gives better results than the low-κ spacers in junctionless transistor [12]. Length of spacer and value of dielectric constant (κ) also play significant role in device performance [13].
Different dielectric spacers with different proportion and configurations can be used for better device characteristics as compared to the conventional FET [14][15][16][17]. Recently, the significant power reduction has been examined in performance of JLT and improved using spacer engineering. Dual-κ spacer length was optimized to improve the subthreshold performance [18]. Impact of Spacer extension length (L ext ) and placement of spacers on only drain side, both sides, only source side on Trigate FET was explored by [19] to enhance the analog performance.
Therefore proposed work is aimed at demonstrating the impact of spacer engineering on junctionless transistor design. The whole work has been carried out by varying L ext , dielectric value of high κ spacer, placement and proportion of dual-κ spacers.
This paper has been divided into following sections: Next Section describes the design setup of the proposed device. In Section 3, various simulated results have been discussed and the conclusion of the work is presented in Section 4.

Design Setup
Junctionless device with dual-κ spacer at 15 nm length of gate (L g ) is designed using Cogenda TCAD software. Height of fin (H fin ) is 20 nm and width of fin (W fin ) is taken as 20 nm and 10 nm. Tungsten with 4.96 eV work function is used for gate terminal. Source region and drain region are doped with concentration of 1 × 10 21 cm −3 while channel doping is 1 × 10 18 cm −3 [20]. Spacer extension length (L ext ) is fixed at 1.5 × L g i.e. 22.5 nm and 2 × L g i.e. 30 nm respectively. The proportion of high-κ material in dual-κ spacers has been taken as 4:1 (L lk :L hk ) 1:4, 3:2, 2:3 where L lk and L hk represents the low-κ and high-κ materials respectively [14].
Equivalent oxide thickness (EOT) [21] is defined in (1) which calculates the values of SiO 2 and HfO 2 thickness as 0.7 and 3.1 nm resulting in overall value of 1.25 nm. SiO 2 has been used as interfacial layer below HfO 2 .
For dual-κ spacers, SiO 2 was used as low − κ material and high-κ material has been changed to 30, 22 Placement of spacers with dual dielectrics is aligned in three formats: (i) on source side, (ii) on drain side, and (iii) on both sides. Figure 1a and b shows the 3D picture of designed junctionless transistor with dual-κ spacers on two sides of gate region for different spacer extension length. Figure 2b shows the internal structure of designed device where fin was covered with EOT.
Selection of fin height/gate length and fin width/gate length has been taken as 1.3 and 0.6 respectively [22]. Being a junctionless device, fabrication of this structure benefits from Fig. 1 3D image of designed junctionless transistor with dual dielectric spacers on both sides in 2:3 ratio for a L ext = 1.5 × L g and b L ext = 2 × L g one reduced step of forming junction. Buried oxide layer is formed on substrate of silicon material. Silicon layer after being formed on BOX, dopants are diffused. Gate oxide stack layer is accumulated, and beneath gate oxide, active fin area is present with sufficient doping and width for full flow of charge carriers. Source and drain regions are placed on the either side of fin. After that, traditional way of fabrication is followed [23].

Simulation Methodology
To check the validation of Cogenda TCAD tool, experimental results obtained by Choi et al. in [20] and simulated results junctionless accumulation mode (JAM) FinFET have been plotted as shown in Fig. 3a which are close in agreement with each other.
Methodology opted for the work as shown in Fig. 3b depicts the step-by-step process.
I ON denoting 'On current' and I OFF denoting 'off current' are calculated at gate supply voltage of 1 V and 0 V respectively while keeping drain supply fixed at 0.05 V. Drain-induced barrier lowering current is measured by (W eff /L g ) × 10 −7 A i.e. 4 × 10 −7 A at V d of 20 mV and 1 V respectively. W eff denotes effective channel width and is defined in Eq. (2) [24].
Lombardi mobility model has been applied to incorporate various factors which contribute towards degradation of mobility of charge carriers. These include scattering mechanisms caused due to surface roughness, phonon and ionized impurities. Matthiessen's rule combines these three factors and accurately assesses its impact. For carrier transport modeling, instead of applying classical model, quantum confinement effects which are dominant in nanoregime, have been incorporated into the classical model [25,26].
Case I. When L ext = 1.5 × L g For this case, spacer extension length (L ext ) has value of 22.5 nm i.e. 1.5 × L g as shown in Fig. 1a.

(a) Effect of variation in spacer placement
In this, dual-κ spacers are kept on the side of source, both sides and on the drain side respectively. Dual-κ spacers on drain side resulted in minimum DIBL of 98 mV/V, output conductance (g d ) of 9.78× 10 −6 S and maximum early voltage (V ea ) of 4.02 V due to improved gate fringing coupling towards the drain side for L ext = 1.5 × L g . However, metrics (i) I ON /I OFF , (ii) subthreshold swing (SS), (iii) transconductance (g m ), (iv) transconductance generation factor (TGF = g m /I d ), (v) intrinsic gain (A v = 20 log (g m /g d )) are better for dual-κ (both sides) structure.       Table 1 shows the device parameters obtained for dual-κ spacer placement along source, both-sides and drain respectively.
Case II. When L ext = 2 × L g Variation in dielectric value of high-κ in dual-κ spacers, placement of dual-κ spacers (source side, both-sides and drain side) and proportion of low and high-κ materials (4:1, 1:4, 3:2 and 2:3) has been implemented taking spacer extension length twice the gate length i.e. 30 nm. For all the cases, simulations have been done and various short channel effects and analog parameters are obtained.

(a) Effect of variation in spacer placement
Out of three cases, dual-κ (both-sides) structure has better performance parameters like I ON , I OFF, I ON / I OFF, SS, g m , TGF, and A v than the other two designed devices for L ext = 2 × L g due to longer effective gate length (L eff ) as shown in Figs. 9 and 10. Performance parameters of Spacer placement along source and drain sides are also shown in Figs. 7, 8, 11, 12 respectively.

(b) Effect of variation in proportion of dual-κ spacers
Simulated results shows that the 2:3 ratio of dual-κ spacers has minimum I OFF of 8.96 × 10 −15 A, maximum I ON /I OFF of order 10 9 and minimum SS of 67.5 mV/dec for lower dielectric value of high-κ material i.e. κ =15 with dual-κ spacers on both-sides.
(c) Effect of variation in high dielectric material For L ext = 2 × L g , improved parameters like I OFF , I ON /I OFF were obtained with dual-κ spacer placement on  both sides for κ =15 as shown in Fig. 9a. High gain of 50.21 dB is achieved for 2:3 proportion as demonstrated in Fig. 10b. Moreover, 112 mV/V value for DIBL is acquired for this ratio with improvement in parameters like early voltage, TGF and higher on-off current ratio than dual-κ (source) and dual-κ (drain) sides (Figs. 11 and 12).

Conclusion and Future Scope
In this work, the influence of spacer engineering in junctionless transistor has been analyzed. The proposed device was designed and simulated using Cogenda TCAD tool at 15 nm gate length. Through this work, effect of varying spacer extension length, placement of dual-κ spacers, proportion of dual-κ spacers and dielectric value of high-κ has  been studied. Simulated results shows that due longer effective gate channel length, dual-κ (both-sides) structure has minimum short channel effects and its other parameters were enhanced from the other two structures. However, dual-κ spacer placement on drain side minimizes the fringing field effect on drain side and this resulted in DIBL of 98 mV/V, V ea of 4.02 V and g d of 9.78 × 10 −6 S. As the proportion of high-κ spacer increases, on-off current ratio and intrinsic gain increase as well as DIBL decrease. For short spacer extension length i.e. 1.5 times gate length, as the dielectric value of high-κ was increased, the short channel effects gets reduced and better performance parameters like I ON , DIBL and A v were obtained. For longer spacer extension length (twice the gate length), improvement in device characteristics such as I OFF of 8.96× 10 −15 A, I ON /I OFF ratio of 0.67× 10 9 , SS of 67.5 mV/dec, TGF of 30.12 V −1 was observed  for low value of high-κ dielectric. Therefore, to get the optimum parameters of the device, a trade-off is required for low leakage applications.
This work can be extended by implementing and analyzing the concept of spacer engineering in rectzoidal fin shaped transistors [27] which proved to be effective in controlling short channel effects and providing better analog performance at nanoscale.