Continuous scaling of MOSFET is being done to achieve high packing density with higher speed. Although scaling has reduced the device size and power consumption, below 20nm it results in fabrication complexity and reduced gate control over channel . Various alternative devices such as SOI, FinFET, TFET, and Junctionless transistors are being used to improve the device performance [2–3]. Numerous channel engineering and gate engineering techniques are used to improve mobility and drive current. High k dielectric gate material, dielectric spacer, dual material gate, nanowire, and nano-tubes have significantly enhanced the gate control over the channel [4–5]. Further, to improve mobility and to reduce the leakage current, charge plasma-based doping-less transistors are getting importance. In this charge plasma technique, the metals of different work functions are used to induce n-type or p-type charged plasma in the semiconductor film.
At smaller dimensions, the fabrication of junction-based devices has become quite complex and costly due to the requirement of abrupt change in doping concentration within a distance of 2–3 nm. This abrupt change in doping requires a millisecond annealing technique. This fast annealing reduces the diffusion of impurity atoms. To resolve this problem, the junctionless transistors are a better choice. In JLTs, there is absence of junction between source channel and channel drain. Since junctions are the primary source of leakage and other short channel effects, this device reflects much improved performance than its junction-based counterparts [6–7]. The JLTs work on the principle of work function difference between gate and channel.
Along with simpler fabrication, this device has following other advantages such as reduced SCEs, high ION/IOFF, nearly ideal subthreshold swing (~ 60 mV/dec), and low series resistance . Double gate structure provides better control of channel from both sides of the channel (top & bottom), resulting in reduced leakage current. Multi-gate devices offer improved mobility, better scalability, higher driving current and better transconductance. Due to the bulk conduction mechanism, JLTs have less effect of surface roughness and defects. This results in much lesser noise and improved reliability [9–10].
To assess the utility and performance of this device in analog circuit applications, three different circuits’ common source amplifier, source follower amplifier, and differential amplifier, are designed. Further, to investigate digital applications, the CMOS inverter is designed and analysed. The common source amplifier is one of the most widely used circuits of all the FET circuit configurations. It provides current and voltage gain along with satisfactory input and output impedance. Source follower amplifiers, also known as common drain amplifiers, are one of the three basic single-stage amplifier configurations. This amplifier circuit provides high input impedance, low output impedance, unity voltage gain, and high bandwidth. The source follower is mainly used for impedance matching in both analog and digital circuits. The differential amplifier is the widely used amplifier circuit where the difference signal is amplified. This amplifier is used in analog circuits for better noise immunity and reduced harmonic. Various performance parameters of amplifier circuits as drain current, transconductance, and voltage gain, are presented in the paper.
Section II contains the device structure and simulation details. The analog circuit applications as common source, source follower and differential amplifier are presented in Section III. Further CMOS inverter using DGJLT is designed and analysed in Section IV, followed by a detailed conclusion in Section V.