Junctionless Gate-all-around Nanowire FET with Asymmetric Spacer for Continued Scaling

In this paper, we have performed the scaling of asymmetric junctionless (JL) SOI nanowire (NW) FET at 10 nm gate length (LG). To study the device electrical performance various DC metrics like SS, DIBL, ION/IOFF ratio are discussed. Even at 5 nm, the device has good electrical properties with subthreshold swing (SS) = ~64 mV/dec, drain induced barrier lowering (DIBL) = ~45 mV/V, and switching ratio (ION/IOFF) = ~106 shows a higher level of electrostatic integrity. At 5 nm LG with optimized spacer dielectric the device exhibits ~5 orders of improvement in IOFF and the improvement is less than ~2 orders at 20 nm LG. Thus, from the result analysis, the spacer dielectrics are essential at lower LG for better performance. For continued scaling, the HfO2 spacer dielectric ensures high performance with the lowest downfall in ION with 11.24% and the decline is 15.8% and 13.26% with no spacer and Si3N4 respectively. With SiO2, Si3N4, and HfO2 spacers the asymmetric spacer ensures an ION/IOFF of ~106 which is permissible for ITRS low power requirements. Moreover, to study scaling flexibility towards analog/RF applications various parameters like transconductance (gm), transconductance generation factor (TGF), total gate capacitance (Cgg), and cutoff frequency (fT) are also determined. Furthermore, the scaling impact on dynamic power (DP) and static power (SP) consumption are also presented. The findings of the study show that asymmetric JL NW FET is one of the potential candidates for future technology nodes.


Introduction
The use of stacked nanowire field-effect transistors (NW-FETs) as a scaling alternative for CMOS technology has been proposed [1]. The Gate-All-Around (GAA) construction provides minimal OFF-current (I OFF ) and a sharp subthreshold slope, while multiple channels stacking results in high drive current (I D ) with a footprint equivalent to FinFET [2]. By arranging channels vertically, NW-FETs have the potential to greatly enhance device density [3]. However, stacking NW present a several technical obstacles. The manufacturing of inner spacers, in particular, has been identified as a possible stumbling point for the technology. To decrease parasitic capacitances, these spacers divide the gate stack between the NW and the highly doped source/drain regions. In critical VLSI system manufacturing [4], NW-FETs could be used to get high yield, and nanosheet and NW thickness can be scaled down to sub-10 nm [5]. So that even with the most aggressive node scaling, the electrical characteristics may be maintained. Inner spacers are now being used in NW-FETs, according to recent research [6]. Moreover, in recent times much attention is kept on junctionless (JL) FETs to continue scaling for the sub-10 nm domain. Compared to conventional inversion mode FETs the JL FETs have the following advantages: (a) It alleviates the thermal budget constraint imposed by the presence of source/drain junctions. (b) Because lateral diffused drain, pocket implantation, and shallow junction are no longer required, the manufacturing flow is simplified. (c) Because the major conducting path is through the highly doped silicon bulk, the interface between the oxide and the semiconductor channel has high immunity to surface scattering [7][8][9].
The need for a spacer between source and drain terminals is fundamental for sub-10 nm technology nodes to overcome SCEs. However, the introduction of spacer raises the series resistance between potentials terminals resulting in decreased I ON . Hence to achieve high performance of a device spacer dielectrics are introduced which boosts I ON and improves subthreshold performance. Moreover, to boost DC, analog/RF metrics i.e., for mixed signal design applications the asymmetric spacer is studied. The introduction of asymmetric spacer leads to the reduction of I OFF by 57% [10]. Moreover, the asymmetric spacer also reduces direct tunneling between channel and drain, and also reduces the feedback miller capacitance effect. By adding extra photolithographic process phases to current technologies asymmetrical devices are developed. Additional photolithographic techniques need more photomasks and exposure equipment, as well as more time in the manufacturing process, raising costs and lowering yield. On the other hand, Cheng et al., developed a method for producing asymmetrical structures that do not require photolithographic steps, thus saving money and time [11].
The following is an analysis of the paper content. The device dimensions and important technological parameters are discussed in Section 2. Section 3 discusses the scaling effects of electrical performance on an asymmetric spacer. Section 4 explains how L G scaling impact analog/RF metrics with various spacer dielectrics.

Device Structure and Simulation Details
The 3-D and 2-D view of JL SOI NW FET is depicted in Fig.  1. The NW FET with gate length, width, and height of 10 nm is considered. The source and drain pad lengths are considered as 20 nm. The SiO 2 with 0.5 nm is considered as interfacial oxide and HfO 2 is 3 nm with EOT of 0.75 nm is maintained and the dimensions and parameters are considered according to ITRS road map which is depicted in Table 2 [12]. The doping for the whole Si channel is 1 × 10 19 cm −3 is maintained. The gate metal work function of 4.8 eV is considered. The optimized source side fin extension of 15 nm and drain side fin extension of 25 nm are maintained to form an asymmetric spacer [9]. The buried oxide is maintained with SiO 2 material. The spacer dielectric is maintained with Air, SiO 2 , Si 3 N 4 , and HfO 2 materials. The device dimensions and parameters used for simulations are listed in Table 1.
The drift-diffusion model was used to simulate the proposed devices, and the following equations were produced by solving the drift-diffusion model, current density expressions, and Poisson equation. These are mathematically referred to as The electron and hole concentrations are denoted by n and p, Ψ is the electrostatic potential of the vacuum level, the ionized doping concentrations are given by N + D and N − A , and the electron charge is given by 'q' respectively. The temperature of the lattice should be consistent throughout the Drift-diffusion scenario.
To accommodate for doping dependent mobility (μ b ) (mobility deterioration owing to surface rough scattering (μ sr ) and acoustic phonon in silicon lattice (μ ac ), the Lombardi unified mobility model was utilized and the total mobility (μ t ) is expressed as: Shockley-Read-Hall (SRH), Auger, and direct recombination were all taken into account using the Carrier recombination model. As a result, final recombination 'U' is equal to The electron and hole quantum correction equation can be written as: Since the schenk's bandgap narrowing model for narrow bandgap effects and the caughey-Thomas model for velocity saturation calculation are used for higher doping. Quantum correction models are used in carrier confinement. The Lucent model is suggested for strong field mobility effects. The Selberherr impact ionisation model is used to calculate the electron-hole pair generation rate. The device is well calibrated with experimental physics and simulated details are presented in Fig. 2.

Result Analysis
On scaling, the comparison of I ON , I OFF , I ON /I OFF , SS, and DIBL characteristics is examined. Scaling L G from 20 nm to 5 nm illustrates, spacer materials influence I D -V GS features. The device obtains decreased I OFF with HfO 2 spacer approaching less than pA range at L G of 5 nm, as shown in Fig. 3a, ensuring further scaling. The decrease in I OFF as the 'k' value increases is because of the increased electric field in the OFF state. The I D , on the other hand, is unaffected by the flat band condition in the ON state, which results in zero electric field. The JL technology enters accumulation mode after a flat band state, and the spacer somewhat improves I D .
Because of increased series resistance and the lack of spacer fringing fields, the device suffers from a greater I OFF when no spacer material is present. As a result, at ultra-scaled L G , spacer dielectric plays a vital role in deciding performance in order to avoid leakages and mitigate SCEs. Except for Air and no spacer dielectric, the device has an I OFF of less than nA for all dielectric spacer combinations at L G = 5 nm. Figure 3b shows the same pattern in I D -V GS , with a 4-order improvement in I OFF as spacer dielectrics are changed. Figure 3c depicts the I D -V GS of 10 nm L G with asymmetric spacer. The device ex-hibits~3 orders improvement in I OFF with HfO 2 spacer. Figure 3d and e show a less than 2 order improvement in I OFF with spacer dielectrics at 14 nm and 20 nm L G compared to other L G due to reduced fringing effects. Because the presence of more effective L G increases gate electrostatic integrity, I OFF is effectively reduced. Furthermore, because of the increased doping in the JL fin extension, the gate fringing fields are unaffected by changes in resistance at higher gate bias, producing in minor variations in I ON and I OFF . Figure 4a depicts the I ON variation with various spacer dielectrics from 20 nm to 5 nm L G . From results it is noticed that the highest I ON is obtained at 5 nm L G with HfO 2 spacer and the lowest with no spacer at 20 nm. For a device the highest I ON represents high performance. With HfO 2 spacer at L G = 5 nm, the device exhibits the highest I ON of 70 μA due to fringe induced barrier lowering effect. The HfO 2 has the lowest I ON reduction of all the spacer combinations, with 11.24%. However, the I ON Fig. 1 (a) 3-D n-channel SOI JL NW FET (b) 2-D cross section view at center of the fin Fig. 2 The calibrated I D -V GS simulation [13] Silicon (2022) 14:7461-7471 deteriorates with scaling effect due to increased effective gate length leading to more electron tunneling distance from source to drain. Figure 4b depicts the V th variation for various spacer dielectrics. The device attains the highest V th with HfO 2 spacer at 20 nm L G , and the lowest with no spacer dielectric at 5 nm L G . Higher V th ensures better subthreshold performance. Increase in L G value enhances V th due to improved gate control over the channel. The device exhibits V th of 0.4 V at L G = 20 nm and 0.35 V at L G = 5 nm. When L G is scaled from 20 nm to 5 nm, the device V th is changed by 53.8% and 16.6% using Si 3 N 4 and HfO 2 spacers, respectively. The results show that the HfO 2 and Si 3 N 4 spacers have the least fluctuation in V th and have the lowest threshold voltage rolloff compared to other spacer dielectrics. Even for lower scaled dimensions the device exhibits better V th which is reasonable for driving logic device applications. Figure 5a depicts the I OFF of asymmetric NW FET with various spacers. The device exhibits the lowest I OFF at L G = 20 nm with HfO 2 spacer. Moreover, the device exhibits the highest I OFF with no spacer at L G = 5 nm. However, with SiO 2 , Si 3 N 4 , and HfO 2 spacers the device exhibits I OFF lesser than nA which is feasible for scaling towards low power applications. Figure 5b depicts the I ON /I OFF of asymmetric NW FET with various spacers. The device exhibits the highest I ON / I OFF with HfO 2 spacer at 20 L G . Moreover, the device shows the lowest ratio at 5 nm with no spacer dielectric. With SiO 2 , Si 3 N 4 , and HfO 2 spacers the asymmetric spacer ensures an I ON /I OFF of~10 6 which is permissible for ITRS low power requirements.
The mathematical expressions of SS and DIBL are given as follows [14,15]: Where V th1 is the threshold voltage at V DS1 of 0.9 V and V th2 is the threshold voltage at V DS2 of 0.04 V. Figure 6a depicts the DIBL performance with scaling from 20 nm down to 5 nm with various spacers. The device exhibits the highest DIBL at 5 nm with no spacer dielectric and the lowest DIBL with HfO 2 spacer at 20 nm L G . Larger value of spacer dielectric reduces DIBL impact due to series connected capacitance. The SS impact of dielectric spacer on NW FET from 20 nm to 5 nm L G is depicted in Fig. 6b. Because of a sudden increase in I OFF , the SS deteriorate with L G scaling. Lower L G causes an increase in drain potential impact over the channel, which causes subthreshold behavior to deteriorate. Moreover, at scaled L G of 5 nm, the device exhibits SS of 65 mV/dec which stays near to thermal limit of 60 mV/dec and thus ensures device drivability for low power applications. Figure 7 depicts the electric field and potential distribution of asymmetric spacer NW FET in the ON state i.e., V DS = 0.9 V and V GS = 1.2 V. In Fig. 7a, due to large spacer distance between the channel and drain, there is less impact of electric field distribution on channel and thus reduces hot carriers, impact ionization and higher tunnelling width. Moreover, in Fig. 7b, the large spacer distance even with high-k spacer reduces potential distribution over channel region. Because of the considerable distance between channel and drain, the asymmetric spacer provides lower drain potential across the channel and minimizes SCEs. The performance of an integrated circuit in terms of speed and density of transistors improves as the feature size in an integrated circuit reduces, leading to the idea of system-on-chip (SOC). The SOC is made up of analog and RF communication circuits combined with memory logic and integrated circuits. The analog and RF communication circuits, as well as memory logic and integrated circuits integration leads to SOC. Fig. 8a depicts the first derivative (g m ) of the transfer characteristics at V DS of 0.9 V. The transconductance (g m ) is an important analog metric which is detrimental in obtaining better gain, amplification and cut-off frequencies [16,17]. The device exhibits maximum peak of g m with 0.119 mS at L G = 20 nm at 1 V and g m with 0.125 mS at L G = 5 nm. The peaks of g m have a window for V GS values between 0.85 and 1 V ensuring potential for low power and high-speed operating capability. Figure 8b depicts the transconductance generation factor (TGF = g m I D ) with L G variation from 5 nm to 20 nm. The TGF is an important metric in determining the power required to obtain high speed with respect to gate bias. The TGF determined how current can be used to achieve a desired g m value [18]. Due to the exponential dependence of I D on V GS in the subthreshold zone, the TGF is constant and high, but it diminishes at high V GS because of mobility deterioration. From the Fig. 8b it is observed that TGF is more at L G = 20 nm and lower at L G = 5 nm. Figure 9 depicts the variation of 'Q' with various L G at V DS = 0.9 V. It is observed that increase in L G , the 'Q' increases due to reduction of SS in higher magnitude compared to rise in g m . The device exhibits a marginal increment in 'Q' with scaling. At 5 nm L G the device exhibits the lowest 'Q' of 1.75 μS-dec/mV and at 20 nm L G it is 1.9 μS-dec/mV. Figure 10a depicts the effect of C gd and C gg on L G variation with respect to V GS at V DS = 0.9 V. The C gg is union of other parasitic capacitances like C gs = C of + C sif and C gd = C of + C dif + C gd, inv . Where, C of is the outer fringing capacitance, C sif /C dif are the source/drain internal dependent inner fringing capacitances and C gd, inv is the bias dependent component. Increases in L G the total capacitance and miller capacitance (C gd ) increases [19]. The device exhibits C gd of 0.9 fF at L G = 20 nm and at L G = 5 nm it shows 0.2 fF which is 4x times reduction. Reduced C gd with scaling ensures minimized power consumption and better transient response.  Figure 10b depicts the effect of C gs and C ox on L G variation with respect to V GS at V DS = 0.9 V. The parasitic capacitance C gs and intrinsic capacitance C ox decreases with L G scaling [20]. The device exhibits C gs of 0.2 fF at L G = 5 nm and 0.1 fF which is 5x times increment. The C ox is the oxide capacitance which is detrimental in calculation of power consumption and dynamic power.
The dynamic power is the power consumption due to charge and discharging cycles. The mathematical expression for dynamic power is (C OX V DD 2 ) [21,22] and is depicted in Fig. 11a. The device shows DP of 0.01fJ at L G = 5 nm and 0.05fJ at L G = 20 nm which is 4x times more. Thus, scaling results decrease in dynamic power and ensures device feasibility for low power applications. The power consumption is the power required to drive the circuit [23]. The power consumption is mathematically expressed as 1 2 C OX V DD 2 À Á [24][25][26] and is depicted in Fig. 11b. The power consumption also reduces with L G scaling. At L G = 5 nm the device exhibits 0.02 fJ and at L G = 20 nm 0.9 fJ which is 4x times higher. The intrinsic delay (τ ≈ C gg V DD I ON ) value is determined at V DD value of 0.9 V [27,28] and is depicted in Fig.  12a. For L G value of 20 nm the device exhibits 'τ' of 3.5 ps and for 5 nm L G the device shows 0.6 ps. A decrease in L G leads to reduced 'τ' due to minimized electron tunnel distance. The cut-off frequency Þ determines the speed of the circuit [29,30]. The f T has an inverse relationship with C gg ) is another important figure of merit for determining overall performance of a device [13] and scaling dependence is shown in Fig. 12c. The device exhibits GBW of 0.09 THz with 5 nm L G and 0.04 THz with 20 nm L G .

Conclusion
The spacer dielectric impact on asymmetric JL SOI NW FET has been studied towards scaling. The analysis reveals that spacer dielectric is predominant and fundamental at lower L G compare to a higher one. The device achieves better I ON , I OFF , I ON /I OFF , SS and DIBL at L G = 20 nm with HfO 2 spacer. However, Si 3 N 4 , and HfO 2 spacers exhibits better overall performance and ensures possibility for scaling towards lower nodes. Moreover, the device exhibits better analog/RF metrics towards scaling. Scaling compresses additional parasitic capacitance effects and thus better τ, f T , and GBW. Scaling also reduces DP and PC and ensures its potential for low power applications. Result analysis shows that the asymmetric spacer outperforms device performance for DC, analog/RF and ensures better option for future scaling.
Acknowledgements The authors thank to the department of Electronics and Communications Engineering, NIT Warangal for providing the TCAD Tools.
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