In this paper we have performed scaling performance of asymmetric junctionless (JL) SOI nanowire FET at 10 nm gate length (LG). To study the device electrical performance various DC metrics like SS, DIBL, ION/IOFF ratio are performed. Even at 5 nm, the device has good electrical properties with subthreshold swing (SS) = 64 mV/dec, drain induced barrier lowering (DIBL) = 45 mV/V, and switching ratio (ION/IOFF) = 106 shows a higher level of electrostatic integrity. Moreover, to study scaling flexibility towards analog/RF applications various parameters like transconductance (I), transconductance generation factor (TGF), total gate capacitance (Cgg), and cutoff frequency (fT) are determined. Furthermore, the dynamic power (DP) and static power (SP) consumption of the device with scaling is also presented. The findings of the study show that asymmetric JL nanowire FET is one of the scaling possibilities.