High-k Dielectric Double Gate Junctionless (DG-JL) MOSFET for Ultra Low Power Applications- Analytical Model

This paper describes the impression of low-k/high-k dielectric on the performance of Double Gate Junction less (DG-JL) MOSFET. An analytical model of the threshold voltage of DG-JLFET has been presented. Poisson’s equation is solved using the parabolic approximation to find out the threshold voltage. The effect of high-k on various performance parameters of N-type DG-JLFET is explored. The comparative analysis has been carried out between conventional gate oxide, multi oxide and high-k oxide in terms of Drain Induced Barrier Lowering (DIBL), threshold voltage, figure of merit (ION/IOFF) and sub-threshold slope (SS). The high-k oxide has shown superlative performance as compared to others. The results are further analyzed for various device structures. The DG-JLFET with HfO2 exhibits excellent attainment by mitigating the Short Channel Effects (SCEs). The significant reduction in off current makes the device suitable for ultra-low power applications. There is a 61.9 % and 34.29 % improvement in the figure of merit and sub-threshold slope in the proposed device as compared to other devices. The simulation of DG-JLFET is carried out using the Silvaco TCAD tool.


Introduction
The MOSFET has been introducing in the field of electronics for more than 50 years. MOSFET is used to make an integrated circuit to act as a switch. Aggressive downscaling of gate oxide leads to more leakage current in the device. The scaling of MOSFET produces new challenges and opportunities for the device engineer. The short channel effects occur at a nanoscale size which mitigates the device performance. Many new device structures have been investigated to reduce the SCEs. Multi-gate devices have been preferred over single gate MOSFET due to their scalability. The necessity of abrupt p-n junctions between source/drain region and channel put the challenges in doping profile technique. Junctionless design is proposed by Colinge et al. [1] The absence of p-n junction between source/drain and the channel region is due to zero doping concentration gradient implies the presence of same doping in source/channel/drain regions increases effective channel length which reduces the short channel effects in Junctionless MOSFET [2][3][4][5][6].
To improve the performance in DG-JLFET for the parameters such as off current, on current, trans-conductance, DIBL and threshold voltage, many gate and channel engineering approaches are adopted [7][8][9][10]. The gate dielectric materials are required mainly for having good insulating properties and high capacitance value [11][12][13]. The gate dielectric materials should be able to prevent the diffusion of dopants. It should have good thermal stability and very good interface adhesion with the substrate. However, the utilization of high-k materials improves the control of the gate and results in the reduction of SCEs along with all the above qualities [14,15]. The Lombardi CVT, Shockley-Read-Hall and Drift-diffusion model is utilized for the mobility, recombination and energy transport during the simulation. The Newton method is used for the numerical solution.
An analytical model of DG-JLFET is presented in Section 2. The numerical solution of DG-JLFET using TCAD is described in Section 3. The comparative analyses of DG-JLFET with SiO 2 , Multi oxide and HfO 2 have been portraits in Section 4.

Analytical Modeling
The cross-sectional view of short channel DG-JLFET is shown in Fig. 1.
The N-type DG-JLFETs at 32nm with (a) SiO 2 as dielectric material (b) Multi oxide (SiO 2 +HfO 2 ) as dielectric material and (c) HfO 2 as dielectric material are shown in Fig. 2.
The Poisson's Equation for the short-channel DGJLFETs is given as The parabolic potential approximation is taken in xdirection [16].
The value of a2 can be found assuming continuity of electric displacement vector we have The relation between the central potential and the surface potential can be represented as The surface potential can be obtained by simplifying the above equation as By putting the value of ΨS from Eq. (6) to Eq. (4) we get Modifying the Eq. (1) from the value obtained in Eq. (7) as The Eq. (8) can be simplified by considering 1/L 2 2 =8C oxide / (4ϵ Si *t Si +C oxide t 2 Si ), ξ 0 = V G -γ 2 and γ 2 = V F -[( N A t Si )/ 2C oxide ]-( N D t 2 Si )/8ϵ Si Here L 2 is the natural length of DG-JLFET, ξ 0 is long channel central potential. The above equation can be simplified as The solution of this differential equation is as The value of a 1 and a 2 can be obtained by using boundary conditions which state that the surface potential is the potential at the Silicon-silicon oxide interface, the electric field at the center of the DG-JLFET should be zero due to its symmetric nature and the electrical displacement vector is continuous Hence the value of a 1 and a 2 are Here the value of β 1 , β 4 , β 3 and β 4 can be specified as After calculating the value of a 1 and a 2 , the expression for analytical relation can be solved. The minimum central potential location can be found by differentiating Eq. (10). The y min is the location of the minimum central potential can be found as [17] As in JLFET, when a gate voltage is equal to threshold voltage the channel starts to open [18][19][20]. Hence at threshold voltage the Ψ 0 (y min )=0. For short-channel DG-JLFETs threshold voltage is given as The analytical modeling solution for the threshold voltage for short channel DG-JLFETs is given by Eq. (21). In the case of long channel DG-JLFETs, the value of β and γ = 0. Hence, the threshold voltage for short channel DG-JLFET tends to ω 2 , which is equal to the threshold voltage obtained for long channel DG-JLFET. The effect of high-k material on Threshold voltage in DG-JLFET has been analyzed.

Results & Discussion
The numerical simulation of DG-JLFET at 32nm technology node is carried out using the Silvaco TCAD tool. The performance of the DG-JLFET device can be further enhanced by introducing high-k dielectric gate materials. The structures considered for numerical simulations are having the gate oxide as SiO 2 , HfO 2 and stack architecture of SiO 2 and HfO 2 . These numerical simulations are done with the intention to analyse the characteristics of the device. The physical thickness of oxide is taken as 2nm (in the case of multi oxide 1nm for SiO 2 and 1nm for HfO 2 ). The work function of both gate materials is taken as 5.2ev. The silicon material is uniformly doped with n-type material with the doping density in the range of 1.5e-19 cm -3 . The permittivity of the HfO 2 is taken as 21 and the permittivity of the SiO 2 is taken as 3.9. The results were obtained using the Atlas device simulator and plotted on   Figure 3 depicts the characteristics of drain current in saturation (high V DS ) on a logarithmic scale for different oxide materials. The characteristics of SiO 2 as the dielectric for gate oxide are shown with the red line, the green line shows the characteristics of multi-oxide as a dielectric material for the gate oxide and the blue line shows the characteristics of HfO 2 as a dielectric material for the gate oxide. It can be seen from Fig. 3 that N-type DG-JLFETs architecture having HfO 2 (oxide permittivity=21) as dielectric material (blue line) has the lowest value of off current. The multi oxide has better off current properties than a device made only with SiO 2 . It can also be observed that the on-current of all the devices is of the same order. The sub-threshold slope of the device can also be deduced from Fig. 3 and the device having HfO 2 as a gate dielectric has the minimum sub-threshold slope among all compared here. The detailed comparisons for the different dielectric materials obtained from numerical simulation are given in Table 1. Table 1 shows the effects of high-k materials/ high-k materials in stack architecture for N-type DG-SOI MOSFET at 32nm. Some of the variations of characteristics parameters are analyzed as under.

DIBL
The Drain Induced Barrier Lowering or DIBL is given by Eq. (Fig. 4).
DG-JLFET with HfO 2 as gate dielectric indicates a lower value of DIBL because of its high value of dielectric constant which in turn enhances the control of gate over the channel and provides low leakage current resulting in lower DIBL.

Threshold Voltage
In JLTFETs when the gate voltage is increased from zero, the channel starts to open. At a particular voltage, the un-depleted region in the middle of the channel vanishes due to the merging of the depleted region; this voltage is called threshold voltage for JLTFETs. It has been observed that at the  Fig. 11 Sub-threshold slope for various MOSFETs structures threshold voltage the inversion layer carrier density is equal to the bulk carrier concentration. The threshold voltage can be represented by Eq. (21). Figure 5 depicts the threshold voltage variation for the different dielectric. The percentage enhancement in threshold voltage is 31.54 % for DG-JLFET with HfO 2 compared to DG-JLFET with SiO 2 and 15.94 % compared to DG-JLFET with Multi oxide. The device with more value of threshold voltage will produce a low leakage current and will be useful for low power applications.

Sub-threshold Slope
The sub-threshold slope (SS) is a significant design parameter related to MOSFET, it is usually described how fast a device can turn off from the on-state. The SS can be calculated as given by Eq. (23) SS depends on the first term only and has a value of 60 mV/ decade [22]. The effect of high-k materials on the subthreshold slope of the 32nm DG-JLFETs is shown in Fig. 6. The percentage improvement in SS is 8.06 % for DG-JLFET with HfO 2 compared to DG-JLFET with SiO 2 and 3.35 % compared to DG-JLFET with Multi oxide. The value of SS is very low points out to a diminution in SCEs.

I ON /I OFF Ratio
The I ON /I OFF ratio is also known as the figure of merit. I ON means the current driving capability of the device and I OFF contribute to the power dissipation. The variation of I ON /I OFF with different dielectric materials for 32nm N-type DG-JLFETs is shown in Fig. 7. Figure 7 depicts DG-JLFETs with SiO 2 dielectric have a smaller value of I ON /I OFF ratio as compared to DG-JLFETs with high-k dielectric materials which can be attributed to the fact that strong depletion of a channel occurs with higher barrier potential in high-k devices [23].
The high-K dielectric mitigates the leakage current in MOSFET. The DG-JLFETs provide better electrostatic control of the gate on the channel. This will enhance the oncurrent of the device. So overall, it will increase the I ON /I OFF value as compared to low dielectric constant materials.

Comparative Analysis
The comparisons of transfer characteristics for all the structures of MOSFET viz. Bulk MOSFET, DG-SOI MOSFET and DG-JLTFET for various oxide viz. SiO 2 , Multi oxide and HfO 2 are shown in Fig. 8.
Comparison of simulation results in Fig. 8 was plotted on the Tonyplot tool of Silvaco. It can be seen from Fig. 8 that the MOSFET made using DG-JLTs will give minimum off current and best slope among all compared for about the same order of on current. The DG-JLT MOSFET having gate dielectric is showing the best characteristics for the off current. Hence, the circuit made with DG-JLT MOSFET is expected to give minimum power dissipation. Figure 9 depicts the I on / I off ratio for various structures having different oxides as a gate dielectric.
It can be seen from Fig. 9 that the MOSFET made with DG-JLT having HfO 2 as dielectric giving a maximum on to off current ratio. A 61.9 % enhancement in I on /I off ratio is envisaged in DG-JLT with HfO 2 in contrast to conventional junction less DG-MOSFET [24]. Figure 10 depicts the DIBL for various structures having different oxides as a gate dielectric. MOS structure made with DG-JLT and DG-SOI having almost the same minimum DIBL among the compared structures. DG-JLT reveals significant mitigation in DIBL as compared to DIBL reported as 0.4965 V by Mohd. Bavir [25] and 0.24 V by P. Wang [26]. This makes the device suitable for ultra-low-power range applications. The results are validated by comparing with existing results. Figure 11 depicts the sub-threshold slope for various structures having different oxides as a gate dielectric. MOS structure made with DG-JLT and DG-SOI having almost the same minimum sub-threshold slope close to perfect (60mv/Decade) among the compared structures. DG-JLT depicts a significant improvement of 7.4 % in SS as compared to SS reported by Mohd. Bavir [25] and 34.29 % by P Wang [26]. It is a clear indication of improvement in the short channel behavior of the device.

Conclusions
The analytical modeling for threshold voltage is developed using parabolic approximation in this paper. The numerical simulation of JLFET is also carried out using TCAD Silvaco. The simulation includes the application of SiO 2, HfO 2 and multi-oxide (SiO 2 +HfO 2 ) as gate dielectric to analyze the characteristics of JLTs. The behavior of DG-JLT was found to be very interesting as compared to bulk and DG-SOI MOSFET. In bulk MOSFET with SiO 2 , I on /I off ratio is 661.86. This ratio increases with an increase in dielectric constant due to the reduction in leakage current. It is scrutinized that the substitution of SiO 2 with high-k dielectric materials in DG-JLT is beneficial for future devices. Moreover, the consequences of SiO 2, HfO 2 and multi-oxide on DG-JLT short channel parameters are studied. HfO 2 as gate oxide reveals a lower value of DIBL and SS as compared to other gate dielectrics on the application of high drain bias.
Further, a comparison has been carried out between bulk, DG-SOI and DG-JLT MOSFET to evaluate the performance of the devices with SiO 2, HfO 2 and multi-oxide. DG-JLT with HfO 2 exhibits excellent immunity against SCEs. The leakage current is a very crucial factor in power dissipation. The leakage current is very less for DG-JLT with HfO 2 that makes it a more appropriate device for ultra-low power applications.
Authors' Contributions The idea of the research was conceptualized by Prashant Kumar and Neeraj Gupta carried out the analytical modeling and simulation of Junctionless MOSFET. The formal analysis and resources for the research were arranged by Munish Vashisht and Rashmi Gupta. Prashant Kumar also prepared the original draft of the paper and Neeraj Gupta did the review, proofreading and necessary editing in the article.
Data Availability The datasets generated and analyzed during the current study are not publicly available but may be available from the corresponding author on reasonable request.

Code Availability
The code used during this work is not available.

Declarations
Conflicts of Interest/Competing Interests The authors declare that there is no conflict of interest regarding the content of this article.
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