The optimized all-optical OR, NOR, NAND gate design contains plasmonic waveguide of refractive index (n) = 2.1 and continuous-waveform (CW) in transverse electric (TE) mode, with wavelength (λ) of 1.55 µm provided at both inputs. The power at input is 0.7e9 W/m and 3e9 W/m for low and high intensity optical signals, respectively. The presented structure is analysed using the FDTD technique and Table 4 shows the parameters of the simulation for the design proposed.
Table 4 The Y-shaped plasmonic OR, NOR, NAND gate power combiner Simulation parameters
Simulation Parameters
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Considered value
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Power at less intensity
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0.7 × 109 W/m
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Power at high intensity
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3 × 109 W/m
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Size of X mesh (μm)
|
0.0114
|
Size of Z mesh (μm)
|
0.0114
|
X mesh cells
|
349
|
Z mesh cells
|
603
|
Transverse Input field
|
Gaussian
|
3. 1 OR gate
Based on truth table of OR logic gate, when both inputs are low, the output is low; otherwise, it generates a high output. The explanation that follows gives details of different inputs and phase changes done to the Y-shape combiner to make it work with the OR outputs. In this instance, both the Y-combiner inputs are provided a signal of less- power intensity 0.7e9 W/m. According to the OR gate truth table, the output power is noted to be low. varied phase of 180° and 0° is given to both input signals resulting in destructive interference and the OR gate output is observed to be low (Y = 0) as shown in Fig. 5(a). For next case, the upper end of combiner is given less- power intensity (0.7e9 W/m) in contrast the lower end of combiner is provided a signal of greater-power intensity (3e9 W/m). A same phase of 180° or 0° is allowed in both inputs resulting in constructive interference thereby the OR gate’s output is high (Y = 1), as illustrated in Fig. 5(b). In contrast to the preceding instance, the upper end of combiner is given a greater intensity (3e9 W/m) whereas the below end is provided a signal of less-intensity power (0.7e9 W/m). Due to constructive interference, high output of OR gate (Y = 1) is achieved as depicted in Fig. 5(c). Finally, the two inputs of power coupler are provided a high intensity power signal (3e9 W/m), same phase of 180° or 0° is provided resulting in constructive interference with high output (Y = 1) as shown in Fig. 5(d).
3.2 NOR Logic Gate
According to the truth table of NOR logic gate, when both inputs are low, the NOR logic gate creates a high output; but provides low output for the rest. The explanation that follows goes into detail into the various inputs and phase shifts used by the Y-shape combiner to meet the NOR output's requirements. In the first instance, both the Y-combiner inputs are provided a signal of less- power intensity 0.7e9 W/m. Same phase of 180° or 0° is given to both input signals resulting in constructive interference and the NOR gate output is observed to be higher (Y = 1) as shown in Fig. 6(a). in the next case, upper end of combiner is given less- power intensity (0.7e9 W/m) in contrast the lower end of combiner is provided a signal of greater-power intensity (3e9 W/m). As in the preceding example, destructive interference will arise, reducing the strength of the output signal. As a result, the NOR gate’s output is low (Y = 0), as illustrated in Fig. 6(b). In contrast to the preceding case, the upper end of combiner is given a greater intensity (3e9 W/m) whereas the below end is provided a signal of less-intensity power (0.7e9 W/m). Due to destructive interference, resulting in low output of NOR gate (Y = 0) as depicted in Fig. 6(c). Finally, the two inputs of power coupler are provided a high intensity power signal (3e9 W/m), The phase for one input is 180° and the other is 0° resulting in destructive interference resulting in low output intensity (Y = 0) as shown in Fig. 6(d).
3.3 NAND Logic Gate
When both inputs are high in a NAND logic gate, the output is low; otherwise, the output is high. An explanation of how the NAND output alters with phase in a Y-shape combiner can be found below. Figure 7 depicts the propagation of light along the proposed NAND gate for the specified input signal pairings using the FDTD method. In the initial state, both the Y-combiner inputs are provided a signal of less- power intensity 0.7e9 W/m. According to the NAND gate truth table, the output power is noted to be high. Same phase of 180° or 0° is given to both input signals resulting in constructive interference and the NAND gate output is observed to be higher (Y = 1) as shown in Fig. 7(a). While in the next case, the upper end of combiner is given less-power intensity (0.7e9 W/m) and in contrast the lower end of combiner is provided a signal of greater-power intensity (3e9 W/m). A same phase of 180° or 0° is allowed in both inputs. As in the preceding example, destructive interference will arise, reducing the strength of the output signal. As a result, the NAND gate’s output is high (Y = 1), as illustrated in Fig. 7(b). In contrast to the preceding instance, the upper end of combiner is given a greater intensity (3e9 W/m) whereas the below end is provided a signal of less-intensity power (0.7e9 W/m). Thereby, due to the same phase, constructive interference will arise, resulting in high output of NAND gate (Y = 1) as depicted in Fig. 7(c). Finally, the two inputs of power coupler are provided a high intensity power signal (3e9 W/m) The phase for one input is 180° and the other is 0° resulting in destructive interference resulting in low output intensity (Y = 0) as shown in Fig. 7(d).