As we have entered the era of the Internet of Things, Big Data, and artificial intelligence, the global need for data processing has exponentially increased in various fields such as medical services, industrial production, and social media. 1-5. Processing large amounts of data requires high-performance and energy-efficient computation, which is a critical factor for a wide range of data-intensive applications. However, current computer systems based on the von Neumann architecture incur significant power consumption and latency because of the speed gap when accessing data between the separated central processing and memory units 6-9. Recently, logic-in-memory (LIM) has been investigated to overcome the architectural limitations of data movement. LIM performs logical operations in a memory unit to eliminate data movement between the logical and memory tasks. Therefore, LIM architecture has the advantages of not only high bandwidth memory, but also highly energy-efficient computing and processing time.
Various LIM devices can be implemented using either charge-based or resistance-based memory. Charge-based memory mainly refers to static random-access memory (SRAM), dynamic RAM (DRAM), and flash memory. Resistance-based memory includes resistive RAM (RRAM), spin-transfer torque magnetoresistive RAM (STT-MRAM), and phase-change memory (PCM). The read/write time, voltage, LIM computation energy/latency, leakage power, and retention for existing charge-or resistance-based memory, as reported in other studies, are listed in Table 1 10-14. In charge-based memory, although SRAM is very fast (~1 ns) and DRAM has high density, they contain volatile memory devices, and hence have high energy needs. Moreover, SRAM-based LIM suffers from chip area overhead because more transistors than in the conventional 6T SRAM cells are required for computing operations 15, 16. Likewise, DRAM-based LIM has the challenges of area and yield due to the limitation of the cell structure 16-18. NAND/ NOR flash memory with a charge-trapping layer can store data long-term. Nevertheless, for LIM operation, it not only has a low read/write time (<103/ <106 ns) and a high operating voltage (<10 V), but also a relatively high computation energy (41.62/ 0.2 nJ) and latency (8421/~500 ns).
New emerging resistance-based memory (RRAM, PCM, and STT-MRAM) has a non-volatile memory (NVM) capability, and LIM based on resistance-based memory has been presented 19-24. However, resistance-based memory has several drawbacks, such as low processing speed, high operating voltage, and fabrication process. Specifically, RRAM-based LIM has inconsistent switching characteristics due to variations in the fabrication process and requires a relatively high voltage (<3 V) to generate a high current compared to conventional volatile memories 24, 25. The PCM-based LIM has a low write speed (~50 ns) compared to other memory devices due to the switching between crystalline and amorphous phases, and a comparatively high operating voltage (<3 V) 26. The STT-MRAM-based LIM has a low chip yield for mass production, low reliability because of stochastic switching, and read disturbances 27. Moreover, resistance-based memory requires new fabrication processes and new materials (not based on CMOS fabrication technology), and it is not yet mature enough to be available for commercial technology/products 18, 28.
In this study, we propose a NAND and NOR LIM composed of silicon nanowire (SiNW) feedback field-effect transistors (FBFETs) to verify universal gate functions, where the configuration of the SiNW FBFETs maintains conventional CMOS logic gates. The SiNW FBFETs utilized in the LIM have demonstrated near-zero subthreshold swings (SS), high speed, low operating voltage, and quasi-nonvolatile memory characteristics based on the positive feedback loop mechanism 29-31. The LIM exhibits a high processing speed close to that of SRAM and DRAM (<5 ns), ultra-low standby power while storing the data, retention characteristics that will retain certain computational logic states without power supply, and relatively low operating voltage (≤2.5 V) compared to flash memory. Furthermore, the LIM exhibits a relatively high density compared with charge-based memory because it implements LIM operation on only four FBFETs without separate storage devices. In terms of consistent switching characteristics, the proposed LIM is superior in terms of controlling the charge carriers in the silicon channel with the gate voltage, and has a simpler fabrication process compatible with CMOS technology. Therefore, the presented LIM can not only reduce fabrication costs but also enable rapid commercialization in the LIM market. Moreover, the presented LIM has comparatively low LIM computation energy (~0.5/ ~0.2 pJ) and latency (~1 ns) compared with the figures-of-merit of LIM using other memory devices. Furthermore, we specifically examined the operations of the NAND and NOR LIM using the newly proposed dynamic voltage-transfer characteristics (VTC). We investigated the feasibility of the NAND and NOR LIM through mixed-mode technology computer-aided design (TCAD) simulations 32.
Schematic of the FBFETs and circuit diagrams of the LIM
Figure 1 shows a schematic view of a single-gated SiNW p-channel FBFET (p-FBFET) and a single-gated SiNW n-channel FBFET (n-FBFET) utilized in the NAND and NOR LIM. The dimensional parameters of the p-FBFET, as shown in Fig. 1a, are a channel length (LCH) of 150 nm, p+ drain and n+ source region lengths of 50 nm, and a silicon channel diameter of 25 nm. The dimensional parameters of the n-FBFET, as shown in Fig. 1b, are an LCH of 200 nm, p+ drain, and n+ source region lengths of 50 nm, and a silicon channel diameter of 15 nm. The non-gated and gated channel lengths are 1/2LCH for both FBFETs. Supplementary Section 1 provides more details on the device dimensional parameters. Figures 1c and 1d show the diagrams and truth tables of the NAND and NOR LIM, respectively, consisting of two n-FBFETs, two p-FBFETs, and a parasitic load capacitor connected to the output node with a capacitance of 10 fF 33, 34. These LIM operations are conducted by applying voltage pulses of supply voltages VDD and VSS (defined as the drain voltage of the p-FBFET and the source voltage of the n-FBFET, respectively), gate input voltage 1 (VIN1), and gate input voltage 2 (VIN2) under dynamic conditions.