During testing utmost all appropriate and suitable strategy needs to be established for consistent fault coverage, improved controllability and observability. The scan chains used in BIST allows some fine control over data propagations that is used as a backdoor to break the security over cryptographic cores. To alleviate these scan-based side-channel attacks, implementing a more inclusive security strategy is required to confuse the attacker and to ensure the key management process which is always a difficult task to task in cryptographic research. In this work for testing AES core Design-for-Testability (DfT) is considered with some random response compaction, bit masking during the scan process. In the proposed scan architecture, scan-based attack does not allow finding out actual computations which are related to the cipher transformations and key sequence. And observing the data through the scan structure is secured. The experimental results validate the potential metrics of the proposed scan model in terms of robustness to the scan attack and penalty gap that exists due to the inclusion of scan designs in AES core. Also investigate the selection of appropriate location points to implement the bit level modification to avoid attack for retrieving a key.