An asynchronous combinational hardware design flow for commercially available XILINX devices is discussed. It consists of logical and technological stages.
At the logical stage, the multi-level logic is optimized using resubstitution procedures. Also, a relaxation procedure is proposed to increase the speed at the reset stage.
The optimization produces non-indicative circuits. The conditions of the distributed indication are formulated and the procedure is proposed.
The technological stage is based on Webpack place and route software. To ensure stability inside a circuit, timing constraints (less strong than proposed in the literature) are formulated and can be easily satisfied. The simulation shows that resulting circuits are hazard-free ones.
A set of benchmarks is processed. Compared to the conventional dual-rail design, the logical optimization reduces the total number of look-up-tables (LUTs) and number of LUTs in a critical path. At the technological stage, the experiments show that before the relaxation, the propagation delay in the set phase is smaller (due to early output) than in the reset phase. It is confirmed that the relaxation increases the speed in the reset phase. Also, the (dynamic) power is higher for the benchmarks optimized for speed.