Figure 2 compares the electrical performance without annealing (black) and with HPDA (red) in FD-SOI pTFET. The SS of pTFET without annealing is 79 mV/dec, and SS with HPDA is 72 mV/dec. The on-current with HPDA also increases by ~ 33% from 4.44 to 5.92 µA, and Vtcc is shifted by − 200 mV, which shows effective passivation by HPDA.

For a single trap, RTN is observed at two discrete levels in the time domain as shown in Fig. 3(a). The time characteristics of RTN exhibit a high or low state in the time domain, denoted by τc and τe, respectively. If the dominant trap sites within a gate oxide have different levels, the current can fluctuate between two or more states, similar to an RTN waveform, due to random trapping or/and de-trapping of carriers within trap centers. The noise PSD of the current fluctuation can be calculated from the time domain data as follows15,

$$\frac{{S}_{ID}}{{I}_{D}^{2}}=\left(\frac{4{\tau }_{r}^{2}}{{\tau }_{t}}\right){\left(\frac{{\Delta }{I}_{D}}{{I}_{D}}\right)}^{2}\left[\frac{1}{1+{\left(2\pi f{\tau }_{r}\right)}^{2}}\right]\frac{{S}_{ID}}{{I}_{D}^{2}}=\left(\frac{4{\tau }_{r}^{2}}{{\tau }_{t}}\right){\left(\frac{{\Delta }{I}_{D}}{{I}_{D}}\right)}^{2}\left[\frac{1}{1+{\left(2\pi f{\tau }_{r}\right)}^{2}}\right] \left(1\right)$$

$${f}_{c}= \frac{1}{2\pi }\left(\frac{1}{{\tau }_{c}}+\frac{1}{{\tau }_{e}}\right) \left(2\right)$$

where *τ**c* is the capture-time constant, which is the time until the electron is captured within a trap site, *τ**e* is the emission time constant, which is the time until the electron is emitted from the trap site, *f* is the frequency, *f**c* is the plateau region or the corner frequency of the Lorentzian spectrum where the noise level is independent of frequency, and *∆I**DS* is the amplitude of the current induced by fluctuation. And they are *τ**r* *= τ**c**τ**e**/(τ**c* *+ τ**e**)* and *τ**t* *= τ**c* *+ τ**e*, respectively.

As shown in Fig. 3(b), the PSD for RTN at two discrete levels has Lorentzian spectrums with a corner frequency (blue or green dash lines). Longer τc is required as the trap moves further away from the channel, and fc is corresponding to the location information of trap sites by (2)15. Interestingly, several fc can be observed with the superposition of different Lorentzian spectrum when multilevel RTN is induced from the number of trap sites. As shown in Fig. 3(b) (black), the PSD without high-pressure annealing has two Lorentzian spectrums. The first of these spectrums is caufslsed by a slow trap site near 20 Hz (fc1, blue, the slow trap), and the second is caused by a fast trap site near 3000 Hz (fc2, green, the fast trap). This means that two trap sites are at different depths within gate oxide near the source/channel junction in FD-SOI pTFET. The PSD with high-pressure annealing, on the other hand, exhibits only a flicker noise characteristic because the dominant trap sites within gate oxide are passivated, as shown in Fig. 3(b) (red), resulting in a uniform spatial distribution of the gate oxide traps.

The improvement of normalized *S**ID**/I**DS**2* at 100 Hz with the HPDA is ~ 79%, as plotted in Fig. 4. The frequency exponent (*γ*) also decreases with the high-pressure annealing, which means that the trap sites within the gate oxide are nearly uniform-distributed in terms of energy and depth16. The *γ* values obtained in our pTFET are in the same range as those obtained for silicon-based devices such as MOSFET16.

Figure 5 and Fig. 6 show the measured time-domain drain current (*I**DS*)-RTN and its corresponding histograms for FD-SOI pTFET without and with the HPDA. The randomly observed *I**DS*-RTN must be statistically analyzed for its distribution, which can be extracted from the histogram17, 18. The *I**DS*-RTN measured for the pTFETs without and with the HPDA is necessary to decouple individual current levels using a change point detection method. The multilevel RTN due to one fast trap site and one slow trap site (an enlarged view of the fast trap site is also illustrated) is observed in Fig. 5(a). And once again, it means the non-uniformity of the trap. The multilevel RTN can also be identified from four overlapping peak points in the histogram that are superposed by multi-Gaussian distribution, as shown in Fig. 5(b). In general, bulk traps (slow traps) that are relatively deep require a long period for τc and τe, whereas shallow interface traps (fast traps) require a short *τ**c* and *τ**e*. The trap depth is connected to the RTN amplitude *(ΔI**D**/I**D**)*, and the larger the RTN amplitude, the further away from the existing trap in the gate oxide.

The variation of drain current induced by slow and fast trap sites are *ΔI**DS1* = 4.030 nA and *ΔI**DS2* = 0.485 nA, respectively. The dominant flicker noise after the HPDA is observed in Fig. 6(a), which means that the typical characteristic of the RTN can no longer be observed. As previously stated, it is consistent with the PSD with HPDA results shown in Fig. 6(b). The amplitude value is *ΔI**DS3* = 1.81 nA after the HPDA, which shows a reduction of *I**DS* amplitude compared with without annealing case. This result indicates that HPDA has a curing effect on both fast and slow trap sites for a wide range of gate oxide depths.

To verify the interface trap density related to the fast trap sites, *N**it* is extracted using the charge pumping method for no-body contact12. The *N**it* can be calculated from *I**CP* in Fig. 7(a) using the following Eq. 12,

$${N}_{it}= \frac{{I}_{cp, max}}{Aq{f}_{p}} \left(3\right)$$

where *I**CP* is the charge pumping current, *A* is the gate area, *q* is the unit charge, and *f**p* is the pulse frequency.

In Fig. 7(b), the *N**it* values without annealing and with the high-pressure hydrogen annealing (HPHA) and HPDA are 3.307 × 1011, 5.559 × 1011, and 4.286 × 1010 cm− 2, respectively. It means that the *N**it* related to the fast trap sites is reduced due to the passivation by HPDA and HPHA.

The slow strap sites is attributed to capture and emission of channel carriers by the trap sites in the gate oxide, which causes a large RTN amplitude as mentioned previously. The trap sites near the tunneling junction contributed to the LFN, pTFET must consider the influence of tunneling junction characteristics as well as channel transportation. It can be absolutely necessary to quantitatively analyze its impact on device design and circuit performance. And the small-signal model proposed in Wan’s paper19 is used to calculate the total PSD in pTFET, in which a tunneling diode and a MOSFET are connected in series. The validity of the accuracy LFN model in FD-SOI TFET was verified in another paper20, and can be calculated as follows,

$$\frac{{S}_{ID}}{{I}_{D}^{2}}={\left(\frac{1}{1+\kappa }\right)}^{2}\left\{ \left(\frac{\beta {\kappa }^{2}}{A}\right){\left(\frac{1}{N}+\alpha \mu \right)}^{2}\frac{1}{f}+\left(\frac{4{\tau }_{r}^{2}}{{\tau }_{t}}\right){\left(\frac{{\Delta }{I}_{D}}{{I}_{D}}\right)}^{2}\left[\frac{1}{1+{\left(2\pi f{\tau }_{r}\right)}^{2}}\right]\right\} \left(4\right)$$

$$\beta =kT\lambda {N}_{t} \left(5\right)$$

where *β* is proportional to the trap density but independent on *|V**GS**|*, *N* is the carrier density in the channel, *α* is the scattering coefficient and *µ* is the carrier defective mobility21. And, *κ = R**C**/R**T*, *R**t* is the tunneling junction resistor, *R**c* is the channel resistor, the pre-factor [*1/(1 + κ)]2(τ**r**2**/τ**t**)* = 5 × 10− 5 Hz− 1, pre-factor [*κ /(1 + κ)]**2**(β/A)[1/N + αµ]**2* = 9 × 10− 9 are assumed to be a constant22. That is, *N**t* can be obtained from (5), where *k* is the Boltzman constant, *T* is the temperature, *λ* is the tunneling attenuation length, respectively.

As shown in Fig. 7(b), the *N**t* without and with HPHA and HPDA is 2.72 × 1018 eV− 1cm− 3, 1.53 × 1018 eV− 1cm− 3, and 6.55 × 1017 eV− 1cm− 3, respectively. It means that the *N**t* related to the slow trap sites is reduced due to being passivating by using the HPDA and HPHA. Therefore, due to the advantage of the reduction of typical noise characteristics of the RTN and the LFN, and thermal budget, the HPHA, and the HPDA are potentially significant and essential for future integrated TFET technology.