Designing and analyzing all-inkjet printed inverters
The most effective approach to designing and testing the all-inkjet printed inverters was graphical analysis of their current-voltage characteristics. The graphical method requires experimental determination of the current-voltage output characteristics of the transistor and resistor. Using Kirchhoff’s second law and the Ohm law, for the resistor in the electric circuit loop shown in Figure 1a we obtain:
UDS=U - IDSR (1)
Equation 1 defines the load line of the transistor. The load line passes through two characteristic points: the first is the supply voltage U marked on the abscissa axis and the second is the short drain and source current (I=U/R) on the ordinate axis. The load line was plotted on the same graph as the transistor current-voltage characteristic (see Figure 1b).
The intersections of the load line with the OTFT output characteristic for UGS = 0 V and UGS = U correspond to the currents IDSmin and IDSmax. Assuming that UIN = UGS and UOUT = UDS, from Figure 1a, Figure 1b, and Equation 1 it follows that
UOUT,1 = U- ∆U1 for UIN,0 = 0V
UOUT,0 = ∆U0 for UIN,1 = U (2)
where
∆U1 = IDSminR
∆U0 = U - IDSmaxR (3)
When the inverter is operating as a gate negator, we strive to ensure that the voltages ΔU0 and ΔU1 are as small as possible (the ratio ΔU/U was close to 1). Otherwise, voltages corresponding logic states “1” (high voltage) and “0” (low voltage) will not be sufficiently separated.
A number of processes were carried out to optimize the printing of individual layers of the device. Each layer of the conductors, semiconductors, and insulators required the development a specially formulated ink and optimization of the processes of printing and curing.
Silver electrodes and conductive pads
The processes of printing and depositing the electrodes and conductive pads were optimized to provide a high-quality printed layer free of defects. Optimization involved changing the printing rate and drop volume, as well as the substrate temperature and the number of active nozzles in the printing head. The waveform controlling the piezoelectric element was tuned. As a result, geometrically continuous conductive silver pads and electrodes were obtained. The most optimal parameters for printing the devices were: 40 µm drop space; 40 °C substrate temperature; three functionally active and stable nozzles; 5 kHz jetting frequency. Analysis of the surface of the electrodes using the AFM technique showed that the electrode roughness was around 30 nm, which is relatively high considering its role as a bottom gate for OTFTs (Figure 2a). For that reason, a dielectric layer printed on top of the gate electrode was required to provide additional planarization.
Dielectric layer
The PVP dielectric was printed with a 20 µm drop space, on 25 °C substrate, using ten nozzles. It was finally obtained after printing two layers, wet-on-wet, with 5 kHz jetting frequency. The polymeric films were around 500 nm thick. Analysis by AFM showed two different types of defects on the film surface: 1) agglomerates (large, light circles) and 2) pinholes (small, black circles) (see Figure S1a in the supplementary materials). To remove the particle agglomerates, three-fold filtration of the ink was applied. Defects the in form of pinholes were considered as critical defects, because when printing S/D electrodes the Ag ink penetrated these holes, causing short circuits. To remove such defects, the printing process was run twice, without any intermediate curing of the first film. The layers printed using this method had thicknesses of around 1 µm and roughness of 1 nm (Figure 2b). Thus, the high surface roughness of the Ag electrodes was not reproduced by the semiconductor layer. To check the dielectric properties of the printed films, Broadband Dielectric Spectroscopy was used. The relative permittivity was measured as a function of the sample temperature and frequency of the signal. Analysis of the real part of the permittivity (er) as a function of the signal frequency showed that the polymeric films had stable permittivity of around 3 across a wide range of frequencies (see Figure S1b in the supplementary materials). This permittivity is typical for polymeric dielectrics. The dependence of er on temperature shows that the relative permittivity remained constant up to 100 °C. This was very advantageous, as the printed layers of organic semiconductors could therefore be annealed at temperatures lower than 100 °C, avoiding deterioration of the properties of the transistors.
Semiconductor layers
Two self-formulated inks containing DPPDTT and P3HT semiconductors were optimized to compare the electronic functionality of the samples. The viscosity of the ink was tuned with reference to its jetting behavior i.e., the shape and trajectory of the droplets generated by the DMC printhead of the DMP-2831 printer. Another comparison was also made to a commercially available ink, FS0096 by Flexink Ltd.21 It was found that the use of toluene as a solvent in the P3HT- and DPPDTT-based inks did not allow for high-quality prints, despite correct drop generation by the printhead. The layers were heterogeneous and discontinuous, with many surface defects. The coffee stain effect was also very prominent (see Figure S2 in the supplementary materials). The coffee stain effect was caused by the accumulation of the polymer on the edges of the drying droplets.22,23 To minimize this problem, O-dichlorobenzene was used to modify the ink composition, as it boils at 180 °C, which is higher than the boiling point (111 °C) of the previously used toluene. For every 10 ml of o-dichlorobenzene, 60 µl of toluene was added to the solvent mixture. Ultimately, all the inks produced contained a semiconductor dissolved in a solvent mixture (o-dichlorobenzene with toluene). The concentration of the organic semiconductor in the solvent mixture was 2 mg/ml.
To inkjet print the semiconductor layer, certain parameters were kept constant. The substrate temperature was 40 °C and the jetting frequency was 5 kHz. To deposit the semiconductor DPPDTT, a drop space of 20 µm was used and the number of the active nozzles was set to 6. To deposit the P3HT layer, up to 10 active nozzles were used and a drop space of 15 µm was applied. The layers printed with the developed inks exhibited smooth surfaces, with a slight accumulation of material at the center-to-bottom right of the layer, caused by the Marangoni effect (Figure 2c).24 In the selected BGBC architecture, the semiconductor layer was positioned as the last layer at the very top. Since its surface therefore did not have to be perfectly flat, no further attempts were made to compensate the unfavorable flow of ink inside the droplet. The thickness of the semiconductor was around 100 nm on the edges and 200 nm at the center. Charge transport occurs only in the first few nanometers of a film, so differences in this range have no impact on charge transport.25
Resistor and transistor
Figure 3a shows a photo of an exemplary matrix of 154 printed transistors on an elastic polymer substrate. The differences between the OTFTs within the array results from their size i.e., the number of inter-comb source and drain electrodes, and hence the width (W) to length (L) ratio of transistor channel (W/L ratio). Dimensions of the printed electrodes and transistors channel, were measured using optical microscopy. Figure 3b shows a schematic arrangement of the individual printed layers. When printing the inter-digitated S/D patterns, it was very important to fix an optimal channel length, which serves as the both functional area for the OTFTs and as the active zone of the resistor.
For channel length L=150 µm, the deviation was ±15 µm, which is very typical for inkjet printing as the ink possesses low viscosity and the substrate’s surface energy is relative high.
All-inkjet printed organic resistors were fabricated with the same inter-digitated electrodes that were used in the transistors, printed directly on the PEN substrate. The active layer of the resistors was made of the P3HT semiconductor. The printed resistors were kept in an ambient and daylight atmosphere for several days. Initially, the shape of the measured DC characteristics was non-linear and changed slowly, but after one week the process stopped. The characteristics reached an ohmic shape with a time-stable slope (Figure 4a), caused by photo-induced oxidation of the P3HT.26 The resistance calculated as a reciprocal of the slope of this line was dependent not only on the area of the P3HT layer (Figure 3c), but also on the molecular weight of the polymer. This enabled the fabrication of a resistor with the desired resistance.
The output characteristics of an all-inkjet-printed OTFT made used DPPDTT and the dependence of the square root of a drain current on its gate-drain voltage are presented in Figure 4b. The electrical parameters extracted from these characteristics are as follows: charge carrier mobility of 2 cm2V -1s‑1, threshold voltage of -9 V, On/Off ratio of around 104. These electrical parameters are comparable with those obtained for OTFTs made by spin-coating a semiconductor with a thermally evaporated gold source and drain electrodes, and are much better than in the case of recently reported all-inkjet-printed OTFTs.15,27,28
The printing conditions were optimized to obtain resistor-transistor pairs that were characterized by the smallest possible voltage ranges DU0 and DU1 (see Figure 1b). Small values for DU0 occurred in transistors with low zero current (IDSmin << IDSmax). However, in order for DU1 to be as small as possible, it was necessary to create resistor-transistor pairs in which the channel resistance of the transistor operating in the linear region (the beginning of the output current-voltage characteristic of the transistor) was much lower than the resistance of the resistor (IDSmax ~ U/R).
Reference inverter
The inverters were analyzed in various combinations of manufactured resistors and transistors. Promising results were obtained for a transistor with a channel length of 150 µm and width of 30 mm. The resistor was printed with electrodes of the same dimensions.
The printed P3HT layer had an area of 0.5 mm2 and the molecular weight of the polymer was 100 kDa.29 The resistance calculated on the basis of the current-voltage characteristic of the resistor was 170 MΩ, and the U/R ratio was −2.35 10‑ 7 A for U = −40 V. Based on these parameters, the load line was obtained for the reference inverter, designed with separately selected printed elements (Figure 5).
The values of the currents IDSmin and IDSmax and the value of the voltages DU1 = 0.4 V and DU0 = 6 V were taken from Figure 5a, and from Equation 2 we obtained UOUT,1 = -39.6 V and UOUT,0 = -6 V. The inverter was characterized by good performance. For gate-source voltage UGS ϵ(Uth,0 V), UDS did not exceed -39 V. When UGS ϵ(-40 V, -30 V), the UDS was in the range (Uth, 0 V). We assume that a Uth range from −9 V to 0 V is a logical zero, and the voltage range from −40 V to −30 V corresponds to a logical one. The lower value of the limit voltage for a logical one (−40 V) is the supply voltage U of the system. The upper limit results from the intersection of the load line for the voltage Uth with the output characteristic of the transistor at UGS = −30 V. In this case, a reference inverter with the current-voltage characteristics shown in Figure 5a will work as a NOT logic gate. The symbol of this a gate is shown in Figure 5b. The key properties of the gate are summarized in Table 1.
Table 1. Truth table for the modeled inverter
UIN [V]
|
Logic
|
UOUT [V]
|
Logic
|
DU/U
|
IDSmax/IDSmin
|
-40 <UGS<-30
|
1
|
-9 <UDS< 0
|
0
|
0.84
|
110
|
-9 <UGS< 0
|
0
|
-40 <UDS< -39
|
1
|
A positive feature was the presence of a threshold voltage in the transistor for which the inequality ïUthï>DU1 occurred. This ensured stable operation of the system, because after applying voltage to the input in the range from −40 V to −39 V the voltage at the gate output was −6 V. After applying the voltage to the input in the range from −9 V to 0 V at the output, we obtained -40 V<UDS<-39 V. Both values of the output voltages were far from the limit values of the logical states.
The considered model of the NOT gate was characterized by resistance to disturbances resulting from accidental voltage changes. This was because the voltage difference between the zero and logical one level was over 80% of the supply voltage value (ΔU/U = 0.84). The relatively large value of the factor IDSmax/IDSmin also protects the device against interference from random noise causing accidental current fluctuations in the output circuit. In relation to IDSmin, the transistor was characterized by a small leakage current (less than 10‑10 A). This facilitated cascading of the devices, since the input current of the NOT gate does not cause a significant change in the current flow in the output circuit of the preceding NOT gates. It should be noted that the possibility of connecting NOT gates is desirable when building most logic circuits (for example, a ring oscillator30).
The model NOT gate described in this work was not constructed in reality. Only the theoretical operation of the device was analyzed. Based on the satisfactory results, it was decided that the ink formulas, geometry of the electrodes, and parameters of the printing process used to create the reference inverter would be applied in fully printed inverters.
Fully printed inverter
Figure 6a shows a six-layer stack of the printed inverters. The transistor and resistor were printed in the same configuration as the separate devices. In the resistor part, the area and molecular weight of the P3HT were matched to the characteristics of the transistor. The channel width of the transistor was adjusted by changing the dimensions of the inter-comb source and drain electrodes.
Figure 6b shows a photograph of the printed device. The P3HT layer (resistor) has an area of 4 mm2. The DPPDTT layer and interdigitated electrodes form a transistor channel with a width of 50 mm and a length of 150 µm.
The same procedure was used to produce the fully printed gates as for the production of the reference inverter. However, different results were obtained. Currents IDSmin and IDSmax and the threshold voltage Uth, were unexpectedly different from those when the devices were printed separately. This was due to the additional printing and annealing processes after printing the organic semiconductor. The already deposited semiconductor layer was subjected to solvent vapor annealing, which changed its morphology and influenced the parameters of the organic transistors. This effect was visible as a change in the color of the P3HT layer during printing of the DPPDTT film. Despite the worse parameters of the transistors and resistors, it was possible to print inverters that were suitable for the construction of NOT gates. An analysis of the operation of these devices is presented below.
We selected the two inverters (INV1 and INV2) with the best parameters of resistor characterized by relatively high resistance compared to the channel resistance of the transistor operating in the linear voltage range (low value DU0). The current-voltage characteristics of the transistors and resistors were detected separately (Figure S3 in the supplementary materials).
Resistors showed linear characteristics in the range of voltages needed for polarization of the inverters. For INV1 it was the range from −50 V to 0 V, and for INV2 from −40 V to 0 V. The resistor area and the transistor channel width in INV2 were much larger than in the transistor in INV1, which contributed to the threefold lower resistance of the resistor (RINV1 = 1.1 GΩ and RINV2 = 250 MΩ) and a drain current higher in INV2 than in INV1 (IDSmaxNV2 = 156 nA and RDSmaxINV2 = 38 nA). Due to the fulfillment of the condition of a small value for DU0, the range of the drain current of the transistors in both devices did not exceed 200 nA (gray rectangles on the output characteristics of the transistors (Figure S3a and S3b). The transistor in INV1 had a threshold voltage of −9 V. In INV2, the threshold voltage in the transistor was 0 V, and the channel resistance was much lower in the “off state” than in the transistor in INV1 (the lower the channel resistance in the off state, the more significantly the transistor off-current increases with higher UDS voltage).
Figure 7a and Figure 7c show load lines plotted with the current-voltage characteristics of the transistors for both inverters which the voltage ranges of the transistor ΔU0 were determined. They were much lower than the voltage ranges ΔU1. This was a result of the relatively large values of the zero currents and the low resistance of the transistor channels in the linear range. The voltage ranges ΔU1 = 11 V for INV1 and ΔU1 = 16.7 V for INV2 were lower than the absolute values of the threshold voltageïUthï. The ΔU/U ratios 0.64 and 0.54, as well as the IDSmax/IDSmin current ratios 3.8and 2.8 for INV1 and INV2, respectively, were less favorable than for the reference inverter (see Table 1).
Figure 7b and Figure 7d show the transfer characteristics UOUT(UIN) of the fabricated inverters.
The U0«1 threshold voltages of the two inverters were determined that corresponded to the condition of equalizing the output voltage and the input voltage of the inverter(UOUT=UIN). The voltage U0«1 corresponds to the limit value of the input and output voltages of the NOT gate, above and below which we have to deal with the logic states zero and one, respectively. Applying the voltage UIN>U0«1 to the input of the system caused the appearance of the voltage UOUT<U0«1 on the output. Conversely, when UIN<U0«1 the voltage UOUT<U0«1 was registered at the output.
In the case of several cascaded interconnected inverters, as shown in Figure 5c, the input and output voltage levels in consecutive devices approach the set values of U0 and U1 as the number of interconnected inverters increases (trace the gray dashed lines and arrows in Figure 7b and 7d). For example, consider inverters connected in a series with electrical properties similar to INV1. Applying 0 V to the input of the first inverter causes −41 V to appear on its output, which will also be the input voltage for the second inverter. A voltage of −9.2 V will appear at the output of the second inverter, and the input of the third inverter, activated with this voltage, will give the output a voltage of about −31 V. At the output of the next inverter, the voltage will be −10 V. Adding more inverters does not change the voltage states much (the black dotted-dashed lines and arrows in Figure 7b). The voltages U0 and U1 on the input and output of every second inverter will be the same. It will also be noticed that the voltage U0 at the output of three or more interconnected inverters will appear with any input voltage in the range from −50 V to −16 V (logical one). Similarly, the voltage U1 appears when the input voltage is in the range from −16 V to 0 V (logical zero). Consequently, it is enough to connect at least 3 inverters in series to obtain a NOT gate with well-defined logical states. Figure 8a shows a schematic diagram of a gate consisting of three inverters connected in series. The transfer characteristics of the NOT1 and NOT2 gates are shown in Figure 8b. Their parameters are summarized in Table 2.
Table 2. Truth table for the inverters
Gate
|
UIN [V]
|
Logic
|
UOUT [V]
|
Logic
|
U [V]
|
NOT1
|
-50<UGS-16
|
1
|
UDS = -10
|
0
|
-50
|
-16<UGS<0
|
0
|
UDS = -31
|
1
|
NOT2
|
-40<UGS<-4.5
|
1
|
UDS = -2.1
|
0
|
-40
|
-4.5<UGS<0
|
0
|
UDS = -8
|
1
|
Analysis of the production and performance of the fully printed NOT gates containing three or more serially connected inverters is beyond the scope of the present study. However, if three or four inverters are printed close to each other, there is a strong chance that the resulting NOT gate will work properly.
Another very important issue is the long-term stability of devices operating under ambient conditions. A potential solution is to encapsulate the devices, which would prevent degradation of the semiconductors and electrodes by oxygen and water. The printed resistors, transistors, and inverters maintained their electrical properties, despite the fact that they were fabricated under ambient conditions and not encapsulated. Figure S4 in the supporting materials shows the current-voltage characteristics of the printed resistor and transistor immediately after their manufacture (Figure S4a) and after three years of storage in air, at room temperature (Figure S4b). The characteristics of the devices do not show significant changes. Only the zero current of the transistor increased. Analyzing the electrical properties of the reference inverter and the inverters INV1 and INV2 shown in Figure 5 and Figure 7, it can be seen that the zero current of the transistor has a key influence on the properties of the inverters. The higher the current, the worse the parameters of the devices. It is worth noting that the zero current of the transistor stored for three years decreased significantly after heating in an oven at 150 °C (Figure S4c). The other properties of the resistor and the transistor did not change, indicating that annealing effectively removed the water from the semiconductor film, preventing the water doping effect. Therefore, the printed inverters do not have to be encapsulated, but only regenerated from time to time at an increased temperature. Encapsulation could even be disadvantageous, because as water and oxygen molecules slowly penetrated the barrier they would also be impeded from escaping the structure. Eventually, the device would be inoperable because the water and oxygen would prevent temperature regeneration.