A. Capacitive Charge Sharing Write-assist Circuit (CCS)
As shown in Fig. 1(a), the Capacitive Charge Sharing write-assist circuit is designed to improve write-ability. Figure 1(b) shows that memory cells have enough cell stability at high voltage levels to hold cell data correctly when VCS is kept at VDD in Phase-1 for inactive WE. After WE assertion, P1 is turned off, and N1 is slightly conducted, so the charge across the source capacitor (CS) is discharged to another capacitor (CBOOST) through N1, as shown in Fig. 1(c); this collapsed voltage (VCS fromVDD to VCOL) can drive and reduce the memory cell's hold-stability as shown in Fig. 2.
As the supply voltage of the cell (VCS) drops, cell stability degrades, as indicated by the "HSNM" stability parameter [5], [8]. For example, when VCS is scaled down, the HSNM of the cell degrades, as shown in Fig. 2.
As shown in Fig. 3, the Q-node of the memory cell is tripped at a swept WL voltage range of 0.46V to 0.61V for a supply voltage (VDD) of 1V. The mean Write Trip Points (WTP) levels are decreased with scaling the supply voltage, which indicates scaling the supply voltage makes the cell unstable and quickly accepts the changes in BIT and BITB lines. So the Q-node of a memory cell is tripped at a sweep WL voltage range of 0.33V to 0.39V for a scaled supply voltage (VDD) of 0.6V. So Write-ability is improved by scaling the SRAM cell's supply voltage, which is done by the CCS write-assist circuit [5], [8], [20], [21].
The WTP voltage occurrence levels are plotted using Monte Carlo simulation, and it was observed that all strong cell samples with high VDD occurred on the right side (at maximum Trip voltage levels). On the other hand, all weak cell samples with scaled VDD occurred on the left side (at minimum Trip voltage levels), as shown in Fig. 4.
B. Tran-Negative BIT Line (T-NBL) Write-Assist Circuit
Tran-NBL write-assist circuit, shown in Fig. 5(c), can improve the write performance with the help of two charging capacitors CRBOOST and CLBOOST. One end of these capacitors is connected to the BIT line and write word line-B(WWLB) of the 9T SRAM cell, and the opposite end of the capacitors is connected to the control input 'BIT_EN' [11], [12], [16].
Figure 6 depicts the timing diagram for the circuit functioning. In a conventional write operation, the active NSEL signal turns both pass-transistors (N1/P1, N2/P2) 'ON' for the whole duration of the WL pulse and BIT, BITB is connected to ground and VDD. Here, 'NSEL' is used for column selection. The NSEL and BIT EN signals are asserted together with the WL Pulse in Tran-NBL, but they are de-asserted halfway through the WL. The pass transistors (N1/P1 and N2/P2) are turned off, leaving BIT and BITB lines floating at the ground and VDD, respectively. Due to capacitive coupling action via capacitors (CLBOOST and CRBOOST), as shown in Fig. 5(a) and Fig. 5(b), the negative transition of BIT_EN produces the bit-line under-shoot (BIT or BITB). Because the floating BIT line at the '0' level generates a momentary negative sudden change voltage on the bit-lines (BIT or BITB). The timing diagram for the write-‘0' operation [6] is shown in Fig. 6. The Tran-NBL write driver circuit generates a negative voltage at the bit line to increase the strength of the accessing transistor (MAXR) to improve the write access speed. The strength of the negative bit voltage depends on selecting boost capacitors CLBOOST and CRBOOST as shown in Fig. 6. Small range capacitors need a small silicon area to fabricate. Such a small range boost capacitor (CLBOOST=110fF) can generate a small negative bit voltage of 110mV, observed in Fig. 6 [16]. The transient negative voltage causes a temporary rise in the access transistor's (MAXR) discharging current, making the Q-node voltage (VQ) pull-down easier. The cross-coupled inverter pairs latch and settle with write data when VQ falls below the trip-point.
During the write-‘1' operation, the column select control input word line-A (WWLA) remains "0", the driver circuit drives BL to "1", and the word line is enabled. As the WWLB is changed to "0" to disconnect the path from the VDD power source by turning off MPDSL, the Q-node storing data "0" is power-gated, which helps raise the voltage at Q-node.
Table I. Minimizing trip voltage levels using column select control voltage V WWLB , which are observed from the voltage transfer characteristics of ST Inverter
VWWLB
|
Feedback Strength
|
Strength of MFBR
|
VTP
|
VDD
|
Strong
|
Very weak
|
593mV
|
Ground
|
Very Weak
|
Strong
|
414mV
|
-ve
|
Zero
|
Very Strong
|
353mV
|
Furthermore, the ST inverter's trip voltage is lower than that of a conventional inverter because the ST inverter's feedback mechanism is decreased with negative VWLB voltage, as shown in Table I. The turned-on MAXR drives the power-gated Q-node to "1", and the ST inverter is switched. After the data in Qb-node is flipped, the column selects WWLB is reset to '1' [22].