To address the aforementioned leakage current problem in the recent devices, new dual chiral CNTFET based two different standard and LECTOR domino OR circuitsare proposed. To differentiate high threshold transistors from low threshold transistors thickness of tube is reduced as shown in Fig. 4(b) and Fig. 6(b).
3.1 Standard Domino CNTFET OR Gate
A generalized circuit diagram for 2 inputs standard footerless domino OR gate is shown in Fig.4(a) having same threshold voltage or single chiral tubes are used whereas Fig.4(b) shows proposed dual chiral footerless domino CNTFET circuit. In dual chiral, carbon nanotube diameters of clock transistor CN1, keeper transistor CN2 and inverter transistor CN4 are varied by changing the chiral vector. Due to this, carbon nanotube diameter reduces and flow of drain current in the transistor also reduces.
The working of a dual chiral CNTFET domino circuit is same as standard domino circuit: when clock is low (clk=L), the high threshold precharge transistor CN1 is ON which charges the dynamic node; this is called precharge phase. During this precharge phase, output node goes low and high threshold CN2 transistor turns ON, maintaining the dynamic node in high state. Output of domino logic is independent of the inputs applied in the evaluation transistors, whereas only the leakage current is dependent on the input vectors applied. On the other hand, when the clk=H, transistor CN1 is OFF and CN2 is dependent on the output of the domino circuit; this is called evaluation phase. Charging of dynamic node will depend on the input vectors applied and according to output node condition which will be low or high. Flow of subthreshold current is shown in Fig.5 using dashed arrow for low and high inputs.
The next subsection presents the LECTOR based dual chiral CNTFET domino circuits to minimize the leakage.
3.2 LECTOR Domino CNTFET OR Gate
In this section LECTOR based 2-input domino OR CNTFET both for single and dual chiral vector is shown in Fig. 6(a) and (b) respectively. Earlier Gupta et al. [6] had presented the same logic for domino logic in CMOS technology for reduction of subthreshold and gate oxide leakage currents. But in case of CNTFET subthreshold leakage is the dominant parameter of the total leakage current, hence the focus of this work is to investigate and reproduce the same logic in case of CNTFET. In Fig. 6(b) dual chiral carbon tubes are used with clock transistor CN1, keeper transistor CN2, inverter transistor CN5 and evaluation transistors CN7 & CN8.
The proposed dual chiral LECTOR domino CNTFET circuit effectively reduces subthreshold leakage power. In this technique, low threshold transistor CN4 and CN6 are leakage control transistors (LCTs) [4]. The proposed dual chiral LECTOR domino gate operates similarly to proposed dual chiral standard footerless CNTFET domino gate. In the proposed circuit, when clock is low (clk=L), the dynamic node is charged through the high threshold transistor CN1 and low threshold transistor CN4. This charging is independent of the input state of previous clock. Suppose the inputs are low before the clk=L, node N2 will be at low potential and low threshold transistor CN4 offers a very low resistance path for charging of the dynamic node. If inputs are high before clk=L, then node N2 potential is not sufficient to turn completely OFF the low potential transistor CN4 (operating near cut-off region). The resistance of CN4 will be less than its OFF resistance which allows charging of the dynamic node. This case is known as precharging phase and output is independent of inputs of the evaluation network, whereas only the leakage current is dependent.
Now, when clk=H or circuit is in standby mode known as evaluation phase.In this phase, output is depending on the inputs. If all the inputs are low, the dynamic node will not be discharged by the evaluation network and the output of the inverter will be low and it turns ON the high threshold transistor CN2, the voltage at node N1 will turn ON the high threshold transistor CN5, but the voltage induced at node N2 will not enough to cut-off the transistor CN4, which will operate near the cut-off region, offering a high resistance path between Vdd and ground, thus reducing subthreshold leakage current.
When all or any one the input is high, the dynamic node will be discharged through the evaluation network. The transistor CN2 will turn OFF the voltage at node N1 and will operate the transistor CN6 near its cut-off region (offering high resistance). The potential at node N2 will turn ON the transistor CN4. Therefore, the introduction of low threshold LCTs increases the resistance between Vdd and ground in addition with propagation delay of the domino circuit. Flow of subthreshold current in dual chiral LECTOR based OR CNTFET for low and high inputs are shown in Fig. 7(a) and (b) respectively. These circuits reduce the leakage current significantly and can be effectively employed for low power designs. The next section presents the efficacy of the proposed work with simulation results.