The overall circuit diagram of the proposed circuit, as shown in the Fig. 4, consists of a simple circuit to set the initial condition of the Henon map followed by the Henon map realization subcircuit, a comparator circuit using LM311D, a monostable multivibrator CD4538BCM and a voltage-controlled SPST switch S2.

The initial condition X0 for the Henon map is set using the resistor R1, Key K1, capacitor C1 and the potentiometer P1. The value of X0 is selected in the range [0,1] by suitably selecting the values of the different components with the switch K1 closed and then fed as the non-inverting input to an operational amplifier U4A that acts as a voltage follower. The output of the voltage follower is fed as the initial condition of the Henon map. Even though two sets of chaotic sequences are generated from Henon map, only one set of chaotic sequences given by [ X0, X1, X2……Xn+1 ] are taken into consideration in this article. Initially, the initial condition X0 and the iterated output X1 are fed to the next stage of the system that forms the iterative circuit.

In the implementation of the iterative circuit, the design of the edge forming circuit forms the crucial part. It is implemented by making use of an operational amplifiers U5A, a comparator U6 using LM311D, a switch, a capacitor C2 and a potentiometer P3.The initial state X0 and the corresponding output state Xn+1 of the Henon map are fed as inverting and non-inverting inputs of the op amp U5A respectively, whereas the output is connected to a capacitor C2 through a potentiometer P3. The voltage across the capacitor C2 is fed as the inverting input to the comparator circuit using LM311 whereas Xn+1 forms the non-inverting input of the comparator.

When Xn+1 is greater than Xn, the op amp U5A outputs a high positive power supply voltage and U6, the comparatot circuit produces a high output voltage level. Now, the capacitor C2 gets charged through the potentiometer P3 and when the voltage across the capacitor rises to Xn+1, which is inturn fed as the inverting input to the comparator U6, it produces a low output voltage. This results in the appearance of a falling edge at the output of the comparator. Similarly, when Xn+1 is lesser than Xn, the op amp U5A produces a low power supply voltage and U6 produces a high voltage level. Now, the capacitor C2 starts to discharge through the generated negative power supply voltage. When the voltage across the capacitor C2 discharges to Xn+1, the output of the comparator U6 rises to high level, thus resulting in the appearance of a rising edge at its output. This output of the comparator LM311 is inturn fed as the trigger input to the monostable multivibrator circuit, which results in the generation of the chaotic pulse train. The generated pulse from the MM is used to close the voltage-controlled SPST switch S2, which inturn passes Xn+1 to Xn. Since, both positive and negative triggering is used to trigger the monoshot, CD4538BCM IC, a dual precision MM is used as the monoshot, which provides two trigger inputs. The pulse width of the generated pulse at the IC output QA, is controllable with the use of external resistor RM and capacitor CM, whose values are designed accordingly. By repeating this process, an iterative process can be thus accomplished.

The time interval between the n th and (n + 1) th pulse is represented by Tn. Based on the charging and discharging principle of capacitors, Tn can be expressed as

**T** **n** **= P****3** **C****2** **ln [ (V****1** **– X****n****) ] / [ (V****1** **– X****n+1****)] if X****n** **< X****n+1** (3)

**= P** **3** **C****2** **ln [ (V****1** **+ X****n****) ] / [ (V****1** **+ X****n+1** **)] else**

where Xn and Xn+1 are represented by Eq. (1) and V1 = 5V, represents the power voltage. From Eq. (3), it is evident that the time interval between the consecutive pulses depends on value of potentiometer P3 and the capacitor C2.