CDR can be classified into two major categories. The first structures are using feedback phase tracking like Phase Locked Loop (PLL) or Delay Locked Loop (DLL). These closed-loop architectures are the most used essentially for their low jitter [1, 2, 5, 6]. The second ones are open loop structures with low power, fast locking time, simple and low-cost design [7].
Open-loop CDR structures aim at local area network, passive optical networks and Serializer/Deserializer applications in which jitter accumulation is not a major problem but need a burst-mode operation to extract a synchronous clock and recover the received data quickly for each asynchronous packet [1, 7, 8, 9].
An open-loop CDR is usually based on a gated oscillator, a high-Q bandpass filter, or an ILO circuit [7]. These circuits are very similar, just one block changes as shown in Fig. 1.
Driven by the recovered clock, the flipflop retimes the incoming data. The variable delay buffer provides an adjustable delay of the input data to align it with the clock edge (the best time is the midpoint of each bit). It can be controlled externally to correct the Process, Temperature, and Voltage (PVT) variations. The edge detector is generally an XOR that will generate pulses at the input data bit frequency that commands the oscillator.
The high-Q filter-based CDR, such as an LC filter, directly samples the clock but its integration on a chip is difficult and there is no input jitter rejection [1, 7]. The gated oscillator circuit aligns this phase by every input data transition, so it also has no input jitter rejection and a strong sensitivity to PVT variations [1].
We propose an ILCDR to enable a fast acquisition time and good jitter tolerance. Indeed, this kind of CDR has an input-jitter-filtering nature as opposed to CDRs based on high-Q filter or gated oscillator [7, 10]. Moreover, when the edge detector output is injected into the ILO, it will force it to lock onto this frequency, allowing some process variation in the oscillator design and thus a better PVT variations tolerance. Indeed, the injection of a periodic signal into an oscillator leads to pulling or locking phenomena [11]. Injection locking means that if an oscillation source is affected by an interference signal whose frequency is very close to its own, its output frequency will be locked at the frequency of the interference signal instead of its own free oscillation frequency [4]. The principle of a simple injection structure is shown in Fig. 2.
A three-stage ring oscillator oscillates at the frequency f0. The introduction of a phase shift ϕ0 in this loop modifies the oscillation frequency because the system phase deviates by a value equal to ϕ0. Figure 2.(b) shows the change in the oscillation frequency from f0 to f1 induced by the effect of ϕ0. Assuming that ϕ0 is generated by an injection voltage V𝑖𝑛𝑗, the system then oscillates at the injection frequency f𝑖𝑛𝑗 [4].
The ILCDR structure can have a closed-loop, generally built with a PLL, to perform a frequency tracking of the input data and adjust the free-running frequency of the ILO as shown in Fig. 3.
This input frequency tracking system improve the BER of the ILCDR in case of a long sequence of 0 or 1 because the difference between the input data frequency and the free running frequency of the ILO is reduced [7]. Adding a PLL increases the complexity, the cost, the die area, and the power consumption of the CDR. In this work, we propose to improve the jitter of the standard architecture of the open-loop ILCDR without adding a PLL to remain in the case of a low-power and low-cost design.