The operation of the proposed gate structure is realized after simulating it by utilising FDTD technique and RSoft FullWAVE simulators. Performance parameters are analyzed by simulating the proposed structure in TE mode. The optical signal amplitude at the output will decide whether the output is logic 1 or logic 0. Intensity of the optical signal larger than 0.5 Pin is considered as logic ‘1’ and less than 0.1 Pin is considered as logic ‘0’. The fraction of ON power level and OFF power level is called contrast ratio for the logic gate and can be calculated by Equation 1.
Where Pon represents the power levels for ‘1’ output and Poff is the power levels for ‘0’ output.
The contrast ratio for the NOT gate of our structure is 8.64dB.
Operating bit rate is obtained by using response time, which can be obtained by observing time taken by the response curve of the output to reach the signal strength from 0 to 90% of the maximum output value. The total time is the addition of delay time (t1) and rise time (t2).
Response time is twice 2t2 and bit rate is determined by taking the inverse of response time
The response time of the NOT gate is
T = 0.26 ps (cT = 80µs) from the output power curve shown in Figure 3.
t1 = 0.13 ps (cT=40 µs)
t2 = 0.13 ps (cT=40µs)
2t2 = 0.26 ps and
Response time is 0.52 ps. If ON-OFF time is same, then bit rate will be 1.88Tbit/s.
a. Results of NOT gate
To realize logic NOT gate, a high control signal is always sent at port A, and input is applied at ports B, port C is not used in this gate. When light signal is not applied to B input (B=0), then input applied at control port couples with cavity and gives output at port Y. The output port obtains a power of Y=0.659 which is considered as logic 1 (ON state). When light input is given at the port B (B=1), then input given at control input A and B interfere destructively and gives the output at the port Y= 0.09 a.u. which is almost logic zero (OFF state).The electrical field intensity and output power for both the input values are shown in Figure 2 & 3. So, contrast ratio = 10log 0.659/0.09 = 8.6dBand the power level of NOT gate reaches 0.659 a.u. and 0.09 a.u. when cT is 80µs and 50µs respectively.
b. Results of AND Gate
The working principle of AND gate is achieved by making a gaussian input light signal to propagate through ports B and C. Output is observed at port Y. Port A is not used in this gate. When both the input B&C is equal to zero there is no output. The electrical field distribution for ‘01’,’10’&’11’ combination of input is shown in Figure 4. When either of B and C is equal to zero, both the inputs interfere destructively and gives the output of Y=0.12 a.u. (OFF state).With both A and B equal to 1, both the inputs interfere constructively and gives the output Y=0.7 a.u. which is considered as logic 1 (ON state) shown in Figure 5.The contrast ratio for AND gate for ‘11’ and ’01,’10’ combination is 7.5dB and all other performance parameters are listed in the Table 1.
Table.1 Simulation Results of proposed 2D PhCs NOT, AND, NOR gates
Input/Output
|
Not gate
|
AND gate
|
NOR gate
|
A
|
1
|
1
|
-
|
-
|
-
|
-
|
1
|
1
|
1
|
1
|
B
|
0
|
1
|
0
|
0
|
1
|
1
|
0
|
0
|
1
|
1
|
C
|
-
|
-
|
0
|
1
|
0
|
1
|
0
|
1
|
0
|
1
|
Y (Ideal output)
|
1
|
0
|
0
|
0
|
0
|
1
|
1
|
0
|
0
|
0
|
Y(actual output) in a.u.
|
0.659
|
0.09
|
0
|
0.09
|
0.09
|
0.7
|
0.68
|
0.18
|
0.18
|
0.18
|
Contrast ratio
|
8.64 dB
|
7.78dB
|
5.77dB
|
Response time
|
0.53ps
|
0.46ps
|
0.66ps
|
Bit rate
|
1.88Tbits/sec
|
2.14Tbits/sec
|
1.55Tbit/sec
|
We have compared the performance of our proposed structure with other logic gate’s structure mentioned in the Table 2 w.r.t. contrast ratio, size, response time and bit rate. We have observed that the size of our structure is reduced and bit rate is also high as compared to other gates. The contrast ratio of NOR gate is comparatively high and other gates is equally good.
Table.2 Performance matrix with comparative study of all the logic gates
Reference
|
Logic gate
|
Contrast ratio
|
Size(no of Silicon rods in x and z direction)
|
Response time
|
Bit rate
|
Rani et al. [11]
|
NOT
AND
|
3.74 dB
11.47 dB
|
45x45
|
2.168 ps
|
0.461 Tb/sec
|
Shaik et al. [22]
|
NOT
AND
NOR
|
11.04 dB
5.81 dB
4.02dB
|
11x9
21x14
21x21
|
0.1052 ps
0.128 ps
0.1336 ps
|
-
|
Anagha et al. [23]
|
AND
|
8.47dB
|
21X21
|
0.246ps
|
|
Hussein et al. [24]
|
AND
|
6.02dB
|
19x21
|
--
|
3.8 Tbps
|
P Rani et al.[25]
|
AND
NOT
NOR
|
8.76 dB
5.42dB
5.42 dB
|
15x15
|
1.024 ps
|
0.976 Tbit/s
|
D’souza et al. [26]
|
NOT
AND
|
23.04 dB
6.02 dB
|
51x23
51x23
|
-
|
-
|
Olyaee et al. [27]
|
NOT
|
43.4dB
|
13x20
|
0.37ps
|
|
Sonth et al. [28]
|
AND
OR
NOT
|
6.1 dB
--
10.21 dB
|
16x19
40x49
31x31
|
0.24 ps
0.128 ps
0.416 ps
|
--
|
Proposed structure
|
NOT
AND
NOR
|
8.6dB
7.8 dB
5.77dB
|
13x13
arrays for all gates
|
0.53ps
0.46ps
0.66ps
|
1.88Tbit/s.
2.14Tbits/sec
1.55Tbit/sec
|