Along with the introduction of Aluminum oxide (Al2O3) comes the introduction of atomic layer deposition (ALD) in the photovoltaic industry. ALD is different from conventional plasma-enhanced chemical vapor deposition tools due to the strict separation of the process gases in two half-cycles during deposition, resulting in a self-limited layer-by-layer growth. The strength of ALD is precisely thickness control and very good deposition uniformity over large area surfaces. Generally speaking, the excellent passivation performance of ALD Al2O3 originates from the combination of low Dit (chemical passivation) and high Qit (field-effect passivation)[23]. The as-deposited thermal ALD Al2O3 usually possesses a relatively low Dit accompanied with a low value of Qit while the as-deposited plasma ALD provides high Dit and high Qit. With extra annealing treatment, both ALD processes show lower Dit ≤ 1×1011 cm-2[24-25]. Regarding the field-effect passivation, the thermal ALD-based Al2O3 film exhibits especially low Qit of the order of 1011 cm-2 before annealing comparing to plasma ALD with Qit of the order of 1012 cm-2. Also, the highest Qit value for plasma ALD can reach 1013 cm-2[26-28] after annealing. Therefore, for the ALD Al2O3 film, Qit can be adjusted from 1×1010~1013 cm-2 by choosing different ALD processes and post-annealing treatment. To investigate the influence of Qit at p-type c-Si/ALD Al2O3 interface on simulated a-PC-p cell’s output parameters, Qit is adjusted from 1×1010~1013 cm-2 with Dit fixed at 1011 cm-2. Fig.2 presents the simulated a-PC-p cell’s output parameters versus Qit. It is seen that the cell’s performance is enhanced with increasing Qit from 1010 cm-2 to 1013 cm-2. In the low Qit (< 1012 cm-2 ) region, the amount of Qit is not enough to assist hole tunneling through the Al2O3 layer, as a result of which low Jsc and low FF appear. When Qit increases from 1012 cm-2 to 1013 cm-2, Jsc and efficiency increase while FF rarely changes. Therefore, it is suspected that enough amount of Qit can ensure the tunneling process even though a dielectric layer is used. This is consistent with the result reported in the literature[28].
As the ALD Al2O3 layer thickness can influence the tunneling of carriers, various levels of Al2O3 layer thickness are adopted to study its effect on simulated a-PC-p cell’s output parameters (shown in Fig.3). To understand how Qit affects the Al2O3 layer of different thicknesses, Al2O3 layers of various thicknesses with and without Qit are introduced (shown in Fig.3). For the Al2O3 layer without Qit, the cell’s FF decreases rapidly from 80.89 % to 49.33 % with Al2O3 thickness increasing from 0.2 nm to 0.4 nm. And FF, Jsc and efficiency are reduced to 40.66 %, 0.32 mA/cm-2 and 0.087 %, respectively, when Al2O3 thickness further increases to 1 nm. However, for the Al2O3 layer with -1013 cm-2 Qit, both FF and efficiency of the cell rarely change even when increasing Al2O3 thickness to 1 nm. This demonstrates the vital role Qit plays in carrier tunneling. When Al2O3 thickness exceeds 1 nm, the cell with -1013 cm-2 Qit loses its Jsc and efficiency rapidly, while its FF still rarely changes. Theoretically, the thicker the Al2O3 layer is, the lower the tunneling probability (T(E)) for carriers will be. Therefore, a thinner Al2O3 is desired for a high tunneling current. Besides, the added Qit facilitates the alignment of the energy bands for both c-Si and a-Si, and causes the accumulation of holes at their interface, which results in a higher built-in potential. Therefore, the enhanced built-in potential facilitates the tunneling of holes through the barrier.
According to the simulated results shown in Fig.2 and Fig.3, Qit at the c-Si/a-Si interface have a significant influence on carrier transport through the Al2O3 dielectric layer. Qit can maintain the successful tunneling of carriers without degrading the cell’s performance. To figure out how Qit influences the transport of carriers through the Al2O3 dielectric layer, band diagram and carrier distribution with the position of two different cells are calculated and compared. The Al2O3 dielectric layer thickness for both cells is fixed at 1 nm. The only difference between the two cells is that one cell has a Qit of -1013 cm-2, while the other has a Qit of 0 cm-2. As shown in Fig.4 (a) and (b), the band diagram of the cell with a Qit of -1013 cm-2 bends upward compared to the other cell, indicating that the high Qit leads to an accumulation of holes at the interface. Fig.4 (c) shows the density of electron and hole at the c-Si/a-Si interface, a large number of holes with an order of 1013 cm-3 accumulated on the c-Si side accompanied by a smaller amount of electrons for the cell with a Qit of 1013 cm-2. Cell with a Qit of 0 only has a much smaller amount of electrons and holes on the c-Si side. This reveals the fact that Qit can influence the carrier distribution at the c-Si/a-Si interface and thus the selective transport of carriers through the dielectric layer. Based on the above three figures, a schematic band diagram illustrating how the charged Al2O3 layer affecting the transport behavior of electrons and holes is shown in Fig.4 (d). As can be seen, the charged Al2O3 layer behaves like a filter which can allow the transport of holes through it with repelling electrons backward.
The oxide bandgap (Eg) can also affect the magnitude of the effect caused by the charges. A difference in the bandgap of Al2O3 has been figured for different deposition processes, there is a variation from 6.2 eV to 7.0 eV was found in the literature[29,30]. In Fig.5, the simulated a-PC-p cell’s four output parameters as a function of the Al2O3 bandgap are shown for Qif value of -1013cm-2. The cell’s efficiency is mainly influenced by the change of Jsc and FF. When Eg is less than 6.7eV, the decrease of efficiency along with increasing Eg is due to the decrease of FF. However, when Eg is bigger than 6.7eV, the loss of efficiency is mostly determined by the decrease of Jsc. It is expected that the barrier height at the c-Si/a-Si interface can be modeled by choosing the Al2O3 layer of different Eg. Therefore, selecting a bigger Eg Al2O3 layer means higher barrier height at the c-Si/a-Si interface, which results in a relatively low tunneling probability, and thus a low FF and a low Jsc.
We know that the interface defect density (Dit) has a great influence on c-Si/a-Si interface recombination. The distribution of Dit at the c-Si/a-Si interface is a state’s superposition near band edges and states. These states include surface pretreatment-induced strain bonds, bonds between adsorbates, dangling bonds, and atoms of different oxide layers leading to several groups of interface states. The minimum value for these interface state distributions can be considered as a measurement of the electronic quality of the wafer and interface. Fig.6 shows the dependence of simulated a-PC-p cells’ output parameters on Dit. As can be seen, the output parameters of a-PC-p cells, whether with or without the charged Al2O3 layer, tend to decrease with increasing Dit. When Dit is less than 1×1013 cm-2, the a-PC-p cell with charged Al2O3 layer possesses a higher efficiency than that without charged Al2O3 layer. However, the tendency operates in the opposite way when Dit is over 1×1013 cm-2, indicating that the Dit can have different effects on cell efficiency for different cells in different Dit regions. As is known to all, Dit at the a-Si/c-Si interface is more than 1×1013 cm-2 and the Al2O3 layer can supply a certain extent of interface passivation. Therefore, the a-PC-p cell’s efficiency can be improved by inserting charged Al2O3 at the a-Si/c-Si interface. Compared with directly deposited a-Si on the c-Si surface, the presence of the charged Al2O3 can reduce Dit and thus higher efficiency can be obtained.
Fig.7 (a) shows a comparison of the I-V characteristics of a simulated cell with only a-Si and with a-Si plus Al2O3 at c-Si/p+ a-Si interface, assuming a fixed interface charge density (Qit) of -1×1013 cm-2. The simulation shows that there is a large efficiency gain (4.2 % relative) when changing from a pure a-Si to a-Si plus Al2O3 (Qit = -1×1013 cm-2) at the c-Si/Al interface. Notably, there is a change of the I-V parameters of the solar cells, i.e., not only an improvement in Voc and Jsc, but also a reduction in FF (see in the inset table in Fig.7 (a)). Voc is improved by reducing the interface recombination within the hole collecting region. Compared with pure p+ a-Si, the addition of a charged Al2O3 layer can reduce a partial portion of Dit by saturating some dangling bonds at the c-Si/p+ a-Si interface (Dit is reduced from 1013 cm-2 to 1011 cm-2). A relative Jsc boost of 5.4 % is observed for the cell with the Al2O3 layer. Comparing the spectral response of simulated cell with only a-Si and with a-Si plus Al2O3 at c-Si/p+ a-Si interface, it is seen that the external quantum efficiency (EQE) increase from 800 nm to 1100 nm (seen in Fig.7 (b)), which is the absorption region of the backside. Below 800 nm, the spectral response is almost the same. In the wavelength region from 800 nm to 1000 nm, EQE increases. As the front side is the same for both cells, the change of EQE between 800 ~ 1000 nm must be due to the insertion of the Al2O3 layer at the c-Si/p+ a-Si interface. It is expected as light in this region is mostly absorbed in the 180 µm thick p-type base, Qit increases built-in potential at c-Si/p+ a-Si interface which ultimately boosts the number of holes collected at the cell’s backside. This can mostly stem from the enhanced interface passivation effect due to the Al2O3 layer. Though a relative FF decrease of 3.0 % occurs, which may be due to the insertion of 1 nm Al2O3 layer, a high FF still maintains in comparison to the Al2O3 layer without Qit (as discussed in Fig.3). As discussed before, the cell with the Al2O3 layer and Qit has a higher built-in potential, and thus enhances hole collection which leads to a relatively high FF.
To evaluate the device performance under various temperatures, the temperature response of the a-PC-p cells with and without charged Al2O3 layer is shown in Fig.8, where the efficiency can also represent the maximum output power. The temperature dependences of Voc, Jsc, FF and efficiency are illustrated by Fig.8 (a)-(d), respectively. As the temperature increases from 26.85 ℃ to 76.85 ℃, Jsc is enhanced; whereas both Voc and efficiency drop; FF fluctuates as the temperature changes. Based on the simulated results, a linear fitting is adopted to calculate the temperature coefficients of Voc, Jsc, FF and efficiency, respectively. The obtained temperature coefficients for both cells are listed in Table 2. As can be seen, the insertion of a charged Al2O3 layer drops the Pmax temperature coefficient from -0.336 % / ℃ to -0.247 % / ℃, indicating that the output power degrades less with increasing working temperature. Simultaneously, the Voc temperature coefficient also drops for the better interface passivation of charged Al2O3 layer. The above results demonstrated a better temperature response for the a-PC-p cell with a charged Al2O3 layer, paving a road for its potential application in high-efficiency and high thermal stability a-PC-p solar cells.
Table 2 Simulated temperature coefficients of Voc, Jsc, FF and efficiency.