Effects of gate length, Lg and channel width, Wc variation on GAA Si NWFET - The effect of different gate lengths on the electrical characteristics of the GAA Si NWFET under study had been investigated where the gate length is varied in the range of 2.5 nm to 4.0 nm. It is apparent from Fig. 2 that as the gate length decreases, the threshold voltage will decrease as well. Reduction of gate length requires less amount of gate voltage to form the inversion layer due to shorter distance between source and drain regions, thus resulting in lower threshold voltage. It can be suggested that by decreasing gate length, the electric field between source and drain become larger, thus violating the proportionate relationship. This leads to velocity saturation and eventually, reduction of drive current. According to Fig. 3(b), current ratio reduces exponentially with decreasing gate length. It implies that downscaling of gate length causes lower drive current, but higher leakage current. Therefore, it is harder to switch OFF the GAA NWFET completely. Downscaling of transistors from classical dimension to quantum scale is needed to govern Moore’s law reality by decreasing the gate length [12]. However, reduction of gate length will affect the device performances whereby it leads to undesired short channel effects, such as the increase of SS and DIBL as presented in Fig. 3(a). GAA NWFET has the highest SS of 134.93mV/dec and DIBL of 221.83mV/V when the gate length is 2.5 nm. The DIBL effect triggers the gate to be ineffective and instigating low controllability on the channel region due to the electrostatic decoupling between source and drain regions [13]. It is suggested also that due to the miniaturization of gate length, the surface-to-volume ratio increases, thus causing surface effect and increment of mean free path of electrons [14]. Additionally, the mobility of charge carriers degrades with increasing of surface scattering [15]. Figure 4 presents the transfer characteristics of the GAA NWFET for different channel widths. The channel width is varied in the range of 3.0 nm to 3.6 nm. Since the drain current is directly proportional to channel width; the narrower the channel region, the lower the drain current is. Furthermore, when the channel width of GAA NWFET decreases, the threshold voltage and current ratio increases while the leakage current, SS and DIBL decreases as shown in Fig. 5 (a) and (b).
Effects of nanowire material variation on GAA NWFET - GAA NWFET is simulated with three different nanowire materials, which are Silicon (Si), Germanium (Ge) and Indium Phosphide (InP). Inevitably, high drive current is desirable in GAA NWFET for high switching speed in digital applications. From Fig. 6, it is apparent that the drive current of GAA InP NWFET is 89.10µA at gate voltage of 2.0V, which is higher as compared to GAA Si NWFET (24.40µA) and GAA Ge FET (56.30µA). Eq. 1 shows the relationship between switching delay and drive current [16]:
$$\tau =\frac{1}{2} \frac{{C}_{sw }\times { V}_{DD}}{{I}_{ON}}$$ (1)
where \(\tau\) is the switching delay, \({C}_{sw }\)is the switching capacitance, \({ V}_{DD}\) is the supply voltage and \({I}_{ON}\) is the drive current where the switching delay is inversely proportional to the drive current. Conductivity of nanowire is affected by the electron mobility of the material and electron drift velocity is directly proportional to electron mobility as shown below:
$${v}_{d}=-{\mu }_{e}E$$ (2)
where \({v}_{d}\) is the electron drift velocity caused by the electric field, \({\mu }_{e}\) is the electron mobility and E is the magnitude of electric field applied to the material. Since InP has the highest electron mobility (5400 cm2V-1S-1) as compared to Si (1400 cm2V-1S-1) and Ge (3900 cm2V-1S-1), the GAA InP NWFET should be highest in terms of drain current. Conversely, high electron mobility characteristic of InP enables it to be controlled by a smaller voltage as compared to germanium and silicon, in producing the same amount of current. It was observed also that the GAA InP NWFET has better overall efficiency, with lower DIBL (128.7mV/V, as compared with GAA Si NWFET and GAA Ge NWFET of 158.42mV/V and 163.58mV/V of DIBL respectively). However, the drawback associated with GAA InP NWFET is the high leakage current with even at low gate voltages as shown in the inset of Fig. 6. It implies that GAA InP NWFET has high power consumption when the device is in OFF state.
Effects of gate oxide variation of GAA NWFET - By replacing the gate oxide with high-κ dielectric materials, gate capacitance can be increased, and leakage current can be reduced [17]. The GAA Si NWFET is simulated with four different gate oxide materials as listed here along with its respective dielectric constants, \({{\epsilon }}_{{r}}\) : Silicon Dioxide, SiO2 (\({{\epsilon }}_{{r}}=3.9)\), and three high-κ dielectric materials, Silicon Nitride, Si3N4 (\({{\epsilon }}_{{r}}=7)\), Aluminium Oxide, Al2O3 (\({{\epsilon }}_{{r}}=9)\) and Hafnium Oxide, HfO2 (\({{\epsilon }}_{{r}}=25)\). It was observed that the GAA NWFET with HfO2 dielectric material had the steepest subthreshold swing curve, thus giving a minimum leakage current of 43.2 pA and smallest DIBL of 137.65 mV/V as presented in Fig. 7(a). The current ratio of the HfO2 is relatively higher as well as compared to the other gate oxides, as observed in Fig. 7(b).
Effects of high-κ coverage angles, θ on the GAA NWFET - In this section, the high-κ dielectric materials (HfO2) coverage on the gate oxide over the channel region is being varied in the range of 0 degrees to 270 degrees. The effect of different high-κ coverage angles on the electrical characteristics of GAA NWFET had been investigated. The transfer characteristics of different high-κ coverage angles are shown in Fig. 8. Figure 9 presents the threshold voltage, current ratio, SS and DIBL for the GAA NWFET at varying high-κ coverage angles. As the high-κ coverage angle of GAA NWFET increases, the threshold voltage and current ratio increases while the leakage current, SS and DIBL decreases. It is found out that 270 degrees wrapping of high-κ dielectric material over the channel region causes reduction of leakage current to 1.35 pA and enhancement of current ratio to 17.7509 x 106. It is suggested that the improvement of device performances for higher high-κ coverage angle is due to better gate electrostatic control over the channel region in GAA NWFET with high-κ dielectric material, which can reduce IOFF at low gate voltages and enhance ION at high gate biases. It is also indicated that when the device was characterized by a steeper subthreshold slope and lower SS, it would exhibit a faster transition between low current and high current. The smaller the value of SS, the faster the ON-OFF state switching speed. According to Fig. 20, SS reduces by increasing the high-κ coverage angle. It is observed that the value of SS is very close to the ideal value of 70mV/dec when the high-κ coverage angle is 270 degrees.
GAA NWFET optimization using Taguchi Method and Pareto ANOVA- The Taguchi method, which is a systematic technique for geometrical and material parameters optimization, was adopted herein to investigate the combined effects of multiple factors with regards to the performance of GAA NWFET, specifically in terms of current ratio and threshold voltage. The standard \({L}_{27}\left({3}^{13}\right)\)orthogonal array was employed, and the percent contribution of each factor was determined by using Pareto Analysis of Variance (ANOVA). In order to achieve low power consumption and high switching speed, the Larger the Better (LTB) characteristic was applied on the current ratio since the device requires a high current ratio performance while the Smaller the Better (STB) characteristic was applied on threshold voltage since the device requires a low threshold voltage performance. The chosen three factors were gate length, channel width and nanowire material which were assigned as A, B and C respectively, as presented in Table 1. The factors were then set at three levels each, ‘0’, ‘1’ and ‘2’ where ‘0’ defines the least value, ‘1’ defines the intermediate value and ‘2’ defines the largest value. To achieve the best combination of gate length, channel width and nanowire material, the GAA NWFET design was simulated with 27 experimental runs. Table 2 presents the actual data for current ratio (ION/IOFF) and threshold voltage (Vth) performances through various simulation, along with the calculated S/N ratio. Table 3 and Table 4 presents the mean S/N ratio for each level of current ratio and threshold voltage performances, respectively.
Table 1
Symbol
|
Factor
|
Level
|
0
|
1
|
2
|
A
|
Gate Length, Lg
|
2.5 nm
|
3.0 nm
|
3.5 nm
|
B
|
Channel Width, Wc
|
3.0 nm
|
3.2 nm
|
3.4 nm
|
C
|
Nanowire Material
|
Si
|
Ge
|
InP
|
Table 2
Simulation Results for Current Ratio and Threshold Voltage with Corresponding S/N Ratio
Exp. Run
|
Factor
|
Simulated Parameters
|
Calculated S/N Ratio
|
A
|
B
|
C
|
ION/IOFF
|
Vth (V)
|
ION/IOFF
|
Vth (V)
|
1
|
0
|
0
|
0
|
944.72
|
0.2262
|
59.51
|
12.91
|
2
|
0
|
1
|
1
|
921.95
|
0.1646
|
59.29
|
15.67
|
3
|
0
|
2
|
2
|
7.13
|
-0.1987
|
17.07
|
14.04
|
4
|
1
|
0
|
0
|
6025.64
|
0.2924
|
75.60
|
10.68
|
5
|
1
|
1
|
1
|
6352.41
|
0.2468
|
76.06
|
12.15
|
6
|
1
|
2
|
2
|
19.86
|
-0.1058
|
25.96
|
19.51
|
7
|
2
|
0
|
0
|
32922.54
|
0.3513
|
90.35
|
9.09
|
8
|
2
|
1
|
1
|
37852.35
|
0.3085
|
91.56
|
10.22
|
9
|
2
|
2
|
2
|
58.03
|
-0.0344
|
35.27
|
29.26
|
10
|
0
|
0
|
1
|
2139.18
|
0.2193
|
66.60
|
13.18
|
11
|
0
|
1
|
2
|
10.29
|
-0.1439
|
20.25
|
16.84
|
12
|
0
|
2
|
0
|
204.00
|
0.1234
|
46.19
|
18.17
|
13
|
1
|
0
|
1
|
15220.59
|
0.2920
|
83.65
|
10.69
|
14
|
1
|
1
|
2
|
31.85
|
-0.0583
|
30.06
|
24.69
|
15
|
1
|
2
|
0
|
1196.08
|
0.2078
|
61.56
|
13.65
|
16
|
2
|
0
|
1
|
92393.74
|
0.3551
|
99.31
|
8.99
|
17
|
2
|
1
|
2
|
99.00
|
0.0056
|
39.91
|
44.97
|
18
|
2
|
2
|
0
|
6294.00
|
0.2695
|
75.98
|
11.39
|
19
|
0
|
0
|
2
|
16.08
|
-0.0892
|
24.12
|
20.99
|
20
|
0
|
1
|
0
|
423.41
|
0.1744
|
52.54
|
15.17
|
21
|
0
|
2
|
1
|
-
|
-
|
-
|
-
|
22
|
1
|
0
|
2
|
54.76
|
-0.0112
|
34.77
|
39.01
|
23
|
1
|
1
|
0
|
2589.85
|
0.2511
|
68.27
|
12.00
|
24
|
1
|
2
|
1
|
-
|
-
|
-
|
-
|
25
|
2
|
0
|
2
|
181.02
|
0.0494
|
45.15
|
26.13
|
26
|
2
|
1
|
0
|
14000.00
|
0.3069
|
82.92
|
10.26
|
27
|
2
|
2
|
1
|
-
|
-
|
-
|
-
|
Table 3
Mean S/N Ratio for Current Ratio
Symbol
|
Factor
|
Mean S/N Ratio
|
Level 0
|
Level 1
|
Level 2
|
Max - Min
|
A
|
Gate Length, Lg
|
43.20
|
56.99
|
70.06
|
26.86
|
B
|
Channel Width, Wc
|
64.34
|
57.87
|
43.67
|
20.67
|
C
|
Nanowire Material
|
68.10
|
79.41
|
30.29
|
37.82
|
Table 4
Mean S/N Ratio for Threshold Voltage
Symbol
|
Factor
|
Mean S/N Ratio
|
Level 0
|
Level 1
|
Level 2
|
Max - Min
|
A
|
Gate Length, Lg
|
15.87
|
17.80
|
18.79
|
2.92
|
B
|
Channel Width, Wc
|
16.85
|
18.00
|
17.67
|
0.82
|
C
|
Nanowire Material
|
12.59
|
11.82
|
26.16
|
13.57
|
Conceptual Signal-To-Noise Ratio (SNR) Approach - The data are then shown graphically in Fig. 10 (a) and Fig. 10(b) of the Conceptual Signal-To-Noise Ratio (SNR) Approach for the current ratio and threshold voltage performances respectively. According to Fig. 10(a), nanowire material (Factor C) and the interaction between channel width and nanowire material (Factor B×C) are highly significant for current ratio performances. Other factors are shown to be insignificant due to each line producing a smaller slope. The B×C two-way table is constructed to select the best combination of channel width and nanowire material, as presented in Table 5. The optimal result obtained for channel width and nanowire material is B0C1. On the other hand, the largest mean S/N ratio obtained is A2 for gate length (Factor A). Hence, the optimal combination to obtain the high current ratio is A2B0C1 within the tested range. Figure 10(b) reveals that the effect of nanowire material (Factor C) and the interaction between gate length and nanowire material (Factor A×C) is more significant for threshold voltage performance. The A×C two-way table is constructed to select the best combination of gate length and nanowire material, as presented in Table 6. The optimal result obtained for gate length and nanowire material is A2C2. On the other hand, the largest mean S/N ratio obtained is B1 for channel width (Factor B). Hence, the optimal combination to obtain the low threshold voltage is A2B1C2 within the tested range.
Table 5
Two-Way Table for Current Ratio
|
B0
|
B1
|
B2
|
Total
|
C0
|
225.46
|
203.72
|
183.73
|
612.91
|
C1
|
249.57
|
226.91
|
0.00
|
476.48
|
C2
|
104.05
|
90.22
|
78.30
|
272.57
|
Total
|
579.07
|
520.86
|
262.02
|
1361.95
|
Table 6
Two-Way Table for Threshold Voltage
|
A0
|
A1
|
A2
|
Total
|
C0
|
46.25
|
36.33
|
30.73
|
113.32
|
C1
|
28.85
|
22.84
|
19.21
|
70.90
|
C2
|
51.87
|
83.21
|
100.36
|
235.44
|
Total
|
126.97
|
142.39
|
150.30
|
419.65
|
Pareto Analysis of Variance (ANOVA) - To validate the results, the percent contribution of gate length, channel width and nanowire material towards current ratio and threshold voltage performances are calculated by using Pareto ANNOVA, as presented in Table 7 and Table 8 for Pareto ANOVA analysis for current ratio and threshold voltage respectively. As shown in Fig. 11 (a) and (b), nanowire material (Factor C) and channel width (Factor B) are found to be the dominant factor for GAA NWFET in terms of current ratio and threshold voltage performances. Thus, the largest value of gate length was selected for both LTB and STB analysis to achieve high current ratio and low threshold voltage performances. Nanowire material (Factor C) has been found to impose the largest effect in LTB analysis for the GAA NWFET design to achieve high current ratio performance by 29.07% and STB analysis for the GAA NWFET design to achieve an optimal threshold voltage by 62.25%. The least value of channel width and the intermediate value of nanowire material are needed to compensate low threshold voltage in LTB analysis. Conversely, the intermediate value of channel width and the largest value of nanowire material are chosen to achieve high current ratio in STB analysis. As a result, the best combination for high current ratio is A2B0C1 while the best combination for low threshold voltage is A2B1C2. With these combinations, an effective current ratio and threshold voltage trade-off for the GAA NWFET can be achieved. Optimizing GAA NWFET with Taguchi Method has shown major improvement as observed. Both the conceptual SNR technique and Pareto ANNOVA approach came to the same conclusions on the dominant factors for current ratio and threshold voltage performances, as presented in Table 9.
Table 7
Pareto ANOVA Analysis for Current Ratio
|
Factor and Interaction
|
|
B x C
|
A
|
B
|
C
|
B x C
|
A x B
|
A x C
|
A x B
|
A x C
|
Sum at Factor Level
|
|
|
|
|
|
|
|
|
|
0
|
530.67
|
345.57
|
579.07
|
612.91
|
315.68
|
452.15
|
439.90
|
435.87
|
438.28
|
1
|
523.51
|
455.92
|
520.86
|
476.48
|
514.69
|
437.34
|
451.66
|
454.41
|
465.94
|
2
|
307.77
|
560.47
|
262.02
|
272.57
|
531.59
|
472.46
|
470.39
|
471.67
|
457.73
|
Sum of Squares of Difference (S)
|
96281
|
69288
|
170901
|
176024
|
86509
|
1865
|
1419
|
1923
|
1211
|
Contribution Ratio (%)
|
15.90
|
11.44
|
28.23
|
29.07
|
14.29
|
0.31
|
0.23
|
0.32
|
0.20
|
Table 8
Pareto ANOVA Analysis for Threshold Voltage
|
Factor and Interaction
|
|
B x C
|
A
|
B
|
C
|
B x C
|
A x B
|
A x C
|
A x B
|
A x C
|
Sum at Factor Level
|
|
|
|
|
|
|
|
|
|
0
|
133.52
|
126.97
|
151.66
|
113.32
|
119.17
|
145.68
|
148.67
|
136.57
|
169.45
|
1
|
162.57
|
142.39
|
161.97
|
70.90
|
167.37
|
148.71
|
165.54
|
125.04
|
142.80
|
2
|
123.56
|
150.30
|
106.02
|
235.44
|
133.11
|
125.27
|
105.44
|
158.04
|
107.41
|
Sum of Squares of Difference (S)
|
2464
|
845
|
5321
|
43784
|
3692
|
975
|
5764
|
1682
|
5812
|
Contribution Ratio (%)
|
3.50
|
1.20
|
7.56
|
62.25
|
5.25
|
1.39
|
8.19
|
2.39
|
8.26
|
Table 9
Comparison of Techniques of Analysis
Best Combinations
|
Conceptual SNR Approach
|
Pareto ANOVA
|
Current Ratio
|
A2B0C1
|
A2B0C1
|
Threshold Voltage
|
A2B1C2
|
A2B1C2
|