Neuron Circuit Post-Layout Simulation
The neuronal circuit simulations are carried out to verify the biological plausible characteristics, including the generation of spike and the adaption of firing frequency. Fig.7 illustrates the variation of membrane voltage (VMEM) corresponding to two different Vthr. With an injection current of 200pA, as Vthr increases, the firing rate of this neuron decreases because it needs to accumulate more charge to reach the neuron's on-threshold.
The Firing frequency versus Input current curve (F-I curve) of the neuron is depicted in Fig.8a. As the input current increases, the output firing frequency increases linearly. It can be seen that the neuron circuit has good linearity at biological frequencies from tens to hundreds of hertz. Figure 8b demonstrates the spike-frequency adaptation behavior, obtained by appropriately tuning the relevant parameters to change current IADP in the K+ block of Fig.5. When IADP reaches the steady state, the neuron spiking frequency remains constant to a lower value compared to the initial one.
Some ports (e.g. Vadp_w, Vrefr_w.) are reserved to adjust the well voltage of the critical P-channel transistors in the neuron circuit. It is expected to precisely control the firing frequency by changing the well voltage. The variations of the firing frequency under the control of various gate and well voltages for MK5 are exhibited in Fig.9. Obviously, the frequency can vary in a wide range when Vrefr increases from 0 to 0.3 V (Fig.9a). Furthermore, given a fixed value Vrefr, the frequency can be calibrated to a precise value by adapting Vrefr_w, as shown in Fig.9b. For example, the Vrefr is fixed to about 0.3 V, if the target firing rate is 30 Hz, then, it can be obtained through regulating Vrefr_w to 0.28 V.
Consequently, the proposed neuron circuit is able to reproduce biologically plausible behaviors and the firing frequency can be precisely controlled by changing the well voltage of the critical PMOS transistors. Neuron’s high energy efficiency and robustness to process variations will be verified in the following sections.
Energy Per Spike
Once proven that the neuron circuit is able to reproduce biologically plausible behaviors, then, this is necessary to evaluate whether it has lower energy consumption at the specified frequency. The energy per spike is equal to:
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where Energy, the total energy consumed, is the product of total power consumed (Power) and simulation time (Time) and Freq is the specified spiking frequency. Comparison of the energy per spike of our proposed neuron with previously published state-of-the-art neuron circuits is listed in Table1. The simulation results of this neuron circuit is compared with both simulation [29-30] and experimental results [28].
Table1: The proposed circuit in comparison with other works.
Work
|
[28]
|
[29]
|
[30]
|
This work
|
Techn.
|
55nm
CMOS
|
28nm
FDSOI
|
22nm
FDSOI
|
55nm
CMOS
|
VDD
|
1V
|
1V
|
0.8V
|
0.3V
|
Area
|
525μm2
|
20μm2
|
900μm2
|
400μm2
|
Results
|
Exp
|
Sim
|
Sim
|
Sim
|
En./spike
|
1.09nJ@
1kHz
|
50pJ@
30Hz
|
850fJ@
1kHz
|
639fJ@
1kHz
|
Compared to a similar circuit [28] in a same technology (55nm CMOS), this design circuit has superiority in area and energy consumption, and consumes energy per spike approximately three orders of magnitude less than the reference neuron at firing rate 1kHz. Moreover, the circuits have an advanced technology (28nm FDSOI) used in [29] and our work have similar structure, however, there is a higher energy consumption at firing rate 30Hz. This is due to the fact that in lower frequencies the inverters spend more time in their high gain region with both transistors conducting, since the VMEM at their input is charging much slower compared to the case with higher frequencies. Therefore, according to the scaling factor, the energy per spike of the circuit proposed in [29] will be similar when scaled to the 1kHz.
The neuron circuit energy consumption at 1kHz firing rate is compared with the more advanced technology neuron proposed in [30], which is one of the most recent mixed-signal silicon neuron circuit designs presented in the literature. The neuron focus on a 22 nm FDSOI process with thick gate oxides and Low-Threshold-Voltage transistors, which allows neuron to operate in low leakage and high performance modes, and the transistor body voltage can be adjusted to reduce the device mismatch and neuron circuit energy consumption. The neuron designed in our work consumes 639fJ@1kHz less energy the similar circuit (850fJ@1kHz) [30].
Process Robustness
For analog neuron circuit, it is greatly affected by process fluctuation. In this circuit, more ports (e.g. VLEAK, Vadp_w) are used to regulate the current in the individual paths, in order to verify the robustness to process variations at extreme process corners (e.g. FF, SS).
Fig.10 demonstrates the robustness of the proposed circuit to process variation. The C-SS and C-FF curves are respectively obtained by adjusting the transconductance between MK5 and ML1, MK3 and ML4 at the corresponding SS and FF process corner. It can be concluded that the frequency deviation of C-SS relative to TT is reduced by 72.6% compared with SS, and C-FF relative to TT is reduced by 70.3% compared with FF. Consequently, the differences between C-SS and TT, C-FF and TT become insignificant, indicating the suppression of process variations by proposed neuronal circuit.
Monte Carlo Analysis
To evaluate the sensitivity of device mismatch in neuron circuit, we ran a series of Monte Carlo simulations. The neuron circuit is performed analysis with 500 runs, with constant injection current, and with bias currents set to obtain a firing rate of approximately 145Hz.
The results of Monte Carlo distribution shows that the neuron’s mean firing rate is centered at 144.81Hz, which is around the expected value145Hz, as shown in Fig.11. Besides, its standard deviation is 3.52 with relative error 2.43%. Compared with reference [29-30], this neuron circuit has lower relative error. Analysis shows that this mismatch is governed by the LEAK block and the K+ block, in particular ML1 and ML5 for the LEAK block and MK5 for the K+ block.