With the advancements in the field of automobile and aerospace, there is a demand for the power electronics and sensors that can reliably operate at high temperature (>200 °C). Generally, silicon (Si)-based bulk complementary metal–oxide–semiconductor (CMOS) is not reliable when the temperature exceed 125°C due to a prominent increased leakage current (thermal runaway).1,2 Simultaneously, a high output current under on-state conditions is also required. Therefore, alternative field-effect transistors (FETs) with a high current on/off ratio at high temperature are desired for low power consumption. A few methods have been proposed to increase the on/off ratio; reducing gate leakage current (IG_leakage) and drain leakage current (ID_leakage) is one way of increasing the ratio. For example, inserting an insulator layer under the gate metal can increase the potential barrier and decrease IG_leakage eventually, or using a high-k gate dielectric to enhance the gate control ability can reduce ID_leakage. Another method is to achieve low on-resistance (RON) to increase output current; for example, increasing carrier mobility and concentration as well as reducing trapping effects can increase output current.
Wide-bandgap semiconductor FETs can reduce the drift region length and increase the doping concentration to increase the output current. Furthermore, it can withstand high voltages and temperatures for achieving a low leakage current; hence, they can easily achieve a high on/off ratio and are more suitable for high-temperature operations compared with Si. Recently, wide bandgap semiconductors, such as gallium nitride (GaN) and silicon carbide (SiC), have been widely used in radio frequency and power applications. To further achieve high reliability and good performance in high temperature applications, ultrawide bandgap semiconductors, such as diamond and gallium oxide (Ga2O3), are gaining attention recently. Compared with Ga2O3, due to the advantages of a high breakdown electric field (>10 MV/cm), excellent thermal conductivity (>22 W·cm−1·K−1), and high carrier mobility (3800 cm2·V−1·s−1 for hole, 4500 cm2·V−1·s−1 for electron)3, diamond has more potential for applications in extreme environments, e.g., high temperature. Interestingly, even without intentional doping, hydrogen-terminated (C–H) diamond exhibits a subsurface two-dimensional hole gas (2DHG) layer via surface adsorbates4,5. However, the 2DHG can be affected by the surrounding environment, inducing instability in the conductivity of the C–H diamonds6,7. Therefore, various dielectrics have been used as gate dielectric layer and passivation layers to enhance the stability of the C–H diamond, such as aluminum oxide (Al2O3)8, hafnium dioxide (HfO2)9, molybdenum oxide (MoO3)10, vanadium oxide (V2O5)11, silicon nitride (SiNx)12, and hexagonal boron nitride (h-BN)13. Among them, C–H diamond metal–insulator–semiconductor FETs (MISFETs) with an Al2O3 dielectric layer have shown many encouraging achievements, including thermal stability14, output current density15, output power density16,17, and cut-off frequency18, suitable for practical applications.
However, the reported maximum on/off ratio for diamond-based devices still remains in the order of 1010; one of the reasons behind this is that the lower limit of leakage current is in the order of 10−8 mA/mm19,20. Moreover, the on/off ratio does not exceed 1 × 107 at a temperature of 200°C14,21, which greatly limits the application of diamond-based devices at high temperature. In addition, when devices are exposed to off-state bias with a relatively high lateral electrical field, it may facilitate the generation of defects or the occurrence of trapping effects22,23, thereby further increasing the RON and leakage currents that decreases the on/off ratio.
Herein, a C–H diamond MISFET with a 40-/100-nm Al2O3/HfO2 stacked passivation layer are proposed to achieve a high on/off ratio. A record-setting on/off ratio of ~1 × 1011 was achieved, with low ID_leakage and IG_leakage in the order of 10−9 mA/mm under off-state conditions at room temperature. Furthermore, a record on/off ratio of ~5 × 109 was achieved at an ambient temperature of 200°C. The electrical characteristics of the C–H diamond MISFETs under off-state conditions were characterized and analyzed. The off-state leakage current characteristics were monitored by time-dependent leakage current measurements. Further, the information on the trapping effects was characterized using pulsed measurements. Finally, the kinetic properties of the traps and their energy level information were obtained using transient RON measurements.
Direct-current I–V characteristics
Figs. 1a,b show the cross-sectional schematic and optical microscopic image of the fabricated C–H diamond MISFET. The details of the device fabrication process are provided in the Methods section and Supplementary Fig. 1. The preliminary direct current drain-current–drain-voltage (ID–VDS) characteristics at room temperature are shown in Fig. 1c. The maximum drain current density (ID_max) and RON were −348 mA/mm, 42.8 Ω·mm, respectively, which are superior to previously reported works with high on/off ratio of ~1010 (refs. 19,20). The preliminary direct current gate-voltage (VGS) dependence of ID, gate-current (IG), and transconductance (gm) characteristics at room temperature are shown in Fig. 1d. The threshold voltage (VTH) and maximum gm were 10.2 V and 32 mS/mm, respectively. The ID_leakage and IG_leakage values were in the order of 10−9 mA/mm under off-state conditions, which are lower than that of previous studies. Benefiting from such low leakage current, an on/off ratio of ~1 × 1011 was achieved in the C–H diamond MISFET, which is the highest value among those of the reported diamond-based devices (Fig. 1e). There are three main reasons for the low leakage current. First, the 40-/100-nm high-k Al2O3/HfO2 introduced fringing capacitances that was conducive to extending the depletion region under off-state conditions, thereby suppressing ID_leakage. Second, the Al2O3/HfO2 stacked layer reduced the electric field at the drain edge of the gate37, causing a reduction in the field-induced leakage current. Third, the good device isolation as well as the relatively-high-quality diamond substrate and dielectric layer.
Although Ren et al. reported an on/off ratio in the order of 1010, after the on/off ratio reached its maximum value, the ID_leakage increased with an increase in gate voltage, resulting in a decreased on/off ratio19,20. This may have been due to the increased IG_leakage caused by the increased gate voltage. However, the on/off ratio of the present C–H diamond MISFETs remained roughly constant at the gate voltage swing of ~4 V (Supplementary Fig. 2). The relatively large gate voltage swing under off-state conditions showed that the C–H diamond MISFET was robust to spurious external signals. Nevertheless, the obtained on/off ratio was still lower than that of GaN-based devices (~1012)38. Furthermore, the subthreshold swing was 0.19 V/dec extracted from the ID–VGS characteristics; it was comparable to that of reported C–H diamond MISFETs20,31 but higher than that of GaN-based devices38. These results may have been caused by the relatively high interface state density (usually ˃1 × 1012 cm−2·eV−1) in C–H diamond MISFETs31,39, which limits further improvement in the on/off ratio and subthreshold swing.
High temperature operation is one of the advantages of diamond-based devices. Fig. 2f shows the direct current ID–VGS characteristics at high temperature conditions. The on/off ratio decreased with the increasing temperature and can be attributed to the effects of high-temperature such as reduced mobility (phonon scattering increase), more severe trapping effects, and increased leakage current. Encouragingly, compared with room temperature, the on/off ratio still remained ~5 × 109 (decreases by only ~20 times) when the temperature is 200°C (Supplementary Fig. 3). This is higher than the previous reported works (Supplementary Table 1), indicating that the C–H diamond MISFETs in this work are capable of operating at high temperature.
Time-dependent off-state leakage characterization
Time-dependent off-state leakage characterization can be used to determine the critical degradation behavior of devices. Here, the leakage currents of the C–H diamond MISFETs were monitored (Methods). When VGS = 14 V, both ID_leakage and IG_leakage barely changed in the VDS range of −10–−22 V (Fig. 2a). However, ID_leakage began to increase with time (~48 s) at VDS = −25 V, whereas IG_leakage did not change significantly. When VGS = 16 V, the leakage currents exhibited a similar trend, whereas the critical breakdown occurred at ~78 s and the magnitude of ID_leakage decreased (Fig. 2b). This implies that a larger gate reverse bias can suppress ID_leakage while also extending the critical breakdown time. Further, the premature breakdown occurred at the Al2O3/diamond interface and/or in the diamond substrate rather than the gate dielectric breakdown. This is mainly due to the generation of defects at the Al2O3/diamond interface and/or in the diamond substrate, which is caused by a high electrical field at the drain edge of the gate under off-state conditions with harsher VDS. Therefore, a reduction in the peak of the electrical field at the drain edge of the gate can mitigate the breakdown by using a high-relative-permittivity and thick passivation layer37.
Pulsed ID–VDS and ID–VGS measurements
Pulsed ID–VDS and ID–VGS characterizations were employed to eliminate heating effects as much as possible and obtain information on the traps (Methods), which reduce the on/off ratio. The measured pulsed ID–VDS and ID–VGS characteristics with a pulse width (PW)/pulse period (PP) = 1 μs/1 ms are shown in Figs. 3a,b. Compared with the quiescent bias condition (VGSQ, VDSQ) = (0 V, 0 V), a negligible change in RON was observed at (VGSQ, VDSQ) = (14 V, 0 V), whereas a distinct increase in RON was observed at harsher VDSQ, as shown in Fig. 3a. This implied that the increase in RON was induced by the trapping effects associated with VDSQ. The first possible explanation is that VDSQ promoted holes to be injected from the gate metal into the stacked passivation layer in the gate–drain access region, i.e., the virtual gate effect40. A second possible explanation is that the high electric field between the gate and drain led to the generation of defects at the Al2O3/diamond interface and/or in the diamond substrate. Interestingly, as shown in Fig. 3b, there was only a modest change in ID_max between the quiescent bias conditions (0 V, 0 V) and (14 V, 0 V) but a distinct increase in VTH at (14 V, 0 V), compared with (0 V, 0 V). A prominent reduction in ID_max and an increase in VTH were observed under harsh VDSQ. However, the unusual increases in VTH (i.e., the increases in the hole concentration) were contrary to those in previous studies, wherein the trapping effects occurred under the gate region, resulting in a decrease in carrier concentration22,41,42.
A hole redistribution model was assumed to explain this unusual phenomenon (Fig. 4a). Under off-state conditions, the detrapping effects mainly occurred under the gate region due to the reverse gate quiescent bias VGSQ, thereby increasing the hole concentration and VTH, which is similar to the time-dependent reverse gate bias stress43. Simultaneously, the trapping effects mainly happened in the gate–drain access region owing to the gate–drain potential caused by the drain quiescent bias VDSQ, which increased the RON. In addition, compared with VDSQ = 0 V, a harsher VDSQ led to a larger ΔVTH because a harsher VDSQ increased the potential between the gate and drain, which is equivalent to an increased gate reverse bias, thus causing more prominent detrapping effects.
To verify the proposed hole redistribution model, a series of pulsed ID–VDS and ID–VGS characterizations were performed as PP was varied from 100 μs to 10 ms while PW was fixed at 1 μs (Supplementary Fig. 4). The changes in RON (ΔRON) and VTH (ΔVTH) at varied PP levels are shown in Figs. 3c,d. It was observed: 1) as PP increased (i.e., stress time increased), ΔRON and ΔVTH increased, indicating that the variation was time-dependent, following the characteristics of time-dependent bias stress measurements, 2) although the ΔVTH increased, the ΔRON increased more significantly, particularly under long PP conditions, indicating that the influence of trapping effects on RON was stronger than that of the detrapping effects, and 3) even if VDSQ = 0 V, the ΔRON slightly increased with an increase in PP at VGSQ = 14 V; this may be attributed to the generation of the interface state. In particular, more interface states were generated when a harsh VDSQ was applied (Supplementary Section A and Supplementary Fig. 5).
To further investigate the impact of the VGSQ and VDSQ on the ΔRON and ΔVTH, two sets of pulsed ID–VDS and ID–VGS with different quiescent bias conditions (VDSQ = 0 and −16 V when VGSQ is varied) were executed (Supplementary Fig. 6). Fig. 3(e) shows a slight increase in ΔRON as VGSQ increased at VDSQ = 0 V, whereas ΔRON significantly increased with increased VGSQ at VDSQ = −16 V. Thus, the increase in RON was mainly due to the trapping effects caused by VDSQ. Fig. 3(f) shows that ΔVTH increased with an increase in VGSQ in both cases of VDSQ = 0 V and VDSQ = −16 V. The increase in ΔVTH was higher at VDSQ = −16 V than at VDSQ = 0 V. Therefore, a high VGSQ led to more significant detrapping effects under the gate region. In particular, VDSQ enhanced the detrapping effects by increasing the potential between the gate and drain.
RON transient measurements
To study the kinetic properties of the traps under off-state conditions, transient RON measurements were performed during off-state stress and corresponding recovery durations (Methods). The change in ΔRON during the off-state stress (under various drain stress conditions) and the corresponding recovery duration are shown in Fig. 5a. ΔRON increased with increasing stress duration and |VDS|. However, upon removing the corresponding off-state stress conditions for 2 s, ΔRON increased dramatically. This unusual increase in ΔRON differed from those obtained in previous studies22,44,45. We speculated that ΔRON increased because the holes were trapped by the gate dielectric layer after removing the off-state stress (Fig. 4b). Transient RON measurements were conducted at a fixed VDS of −16 V and varied VGSs. As shown in Fig. 5b, ΔRON increased with increasing stress duration and VGS. Upon removing the corresponding off-state stress condition for 2 s, a distinct increase in ΔRON was noted, and this increase was linearly related to the increase in VGS (inset, Fig. 5b). These results confirmed that the increase in ΔRON after removing the off-state stress was predominantly caused by the trapping effects under the gate region.
The properties of the trap levels, which are responsible for the on/off ratio decrease under off-state stress conditions, were investigated via transient RON measurements at different temperatures. The recovery of RON after applying (VGS, VDS) = (16 V, −16 V) for 100 s at different temperatures was monitored. Fig. 5c shows the recovery of RON and its corresponding fitting curve (details of the modified kinetic model used for fitting are provided in Supplementary Section B). A larger ΔRON and recovery rate were observed when the C–H diamond MISFET was exposed at higher temperatures, indicating that it was thermally activated. The change in RON can be fitted with stretched exponential kinetics, indicating that the traps had a broad distribution of energy levels46. The Arrhenius plot is shown in Fig. 5d; different activation energies (Ea1 = 0.28 eV and Ea2 = 0.24 eV) were obtained, which were responsible for the decrease in the on/off ratio. In particular, Ea1 was primarily related to the trapping effects under the off-state condition that occurred in the gate–drain access region and under the gate region. Ea2 was mainly associated with the detrapping effects under the off-state condition that occurred under the gate region. The detrapping effects related to the traps with Ea1 = 0.28 eV had a higher activation energy and a larger time constant than those of the trapping effects related to the traps with Ea2 = 0.24 eV (under recovery conditions). The relatively large time constant may have been due to the two following main reasons. First, the holes trapped in the traps of the gate dielectric exerted repulsive electrostatic forces on the holes in the stacked passivation layer of the gate–drain access region to hinder the latter from detrapping. Second, the length of the gate–drain access region exceeded the thickness of the gate dielectric layer, thereby increasing the time to detrapping.