200-mm wafer scale integration of high performance polycrystalline MoS2 thin film transistors

doi:10.21203/rs.3.rs-2999808/v1

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200-mm wafer scale integration of high performance polycrystalline MoS₂ thin film transistors

https://doi.org/10.21203/rs.3.rs-2999808/v1

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published 24 Apr, 2024

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The demand for high-performance thin-film transistors (TFTs) has increased significantly due to the increasing functionalities of electronic devices, such as displays, sensors, and computing platforms. The requirements for TFTs have also become more stringent because future electronic products necessitate denser device arrays, lower power consumption, higher mechanical flexibility, and lower-temperature processing without compromising their performance. To meet these demands, two-dimensional (2D) semiconductors are an ideal solution due to their excellent scalability, transferability, atomically thin thickness, and relatively high carrier mobility. Nevertheless, studies on 2D materials have been limited to small laboratory-scale demonstrations, focusing on proof-of-concept devices with single-crystalline 2D films. In this study, we present industrialization strategies specifically designed for polycrystalline MoS₂ TFTs on a 200-mm wafer scale. We achieved nearly 100% device yield across the wafer by processing it in one of the Samsung's 200-mm fabrication facilities. We find that the metal-semiconductor junction in polycrystalline 2D MoS₂ is fundamentally different from that in its single-crystalline counterpart. Thus, we redesigned the process flow to nearly eliminate the Schottky barrier height at the MoS₂-metal contact, yielding excellent FET performance equivalent to that of state-of-the-art FETs fabricated from single-crystalline flakes.

Physical sciences/Materials science/Materials for devices/Electronic devices

Physical sciences/Nanoscience and technology/Nanoscale devices/Electronic devices

Physical sciences/Engineering/Electrical and electronic engineering

The industry is exploring the possibility of two-dimensional (2D) semiconductors to implant them in integrated circuits for high-performance computing, where further physical scaling of state-of-the-art field-effect transistors (FETs) is necessary.^1–4 2D semiconductors, such as transition metal dichalcogenides (TMDs), have been considered as promising channel materials for next-generation high-performance computing due to their extremely small characteristic length.⁵ Although the uniform large-scale growth of single-crystalline TMDs is still challenging, polycrystalline monolayer TMDs can be grown in large scale with moderate quality, enabling fabrication of thin film transistors (TFTs) for modern electronic and optoelectronic products.^6–10 Especially, scalability of the TFTs meets the current scale-down requirement for back-plane circuits, as the density of the functional front-plane is increasing. Moreover, polycrystalline TMD (poly-TMD) semiconductors are superior to other channel materials, such as amorphous and polycrystalline Si (a- and poly-Si), oxide and organic semiconductors, and carbon nanotubes (CNTs), as shown in Fig. 1a.¹¹ Compared to poly-TMDs, low temperature poly-Si (LTPS) has more non-uniformity in threshold voltages and channel protrusion from the grain boundaries, which limit its applications.^12,13 The limitation of scaling down arises from the fact that such non-uniformity intensifies as the channel size decreases. Furthermore, the atomic thinness and flexibility of poly-TMD TFTs make them suitable for modern flexible/wearable/conformable electronic products,¹⁴ and their weak bonding nature allows for the transfer to arbitrary structures, enabling their integration with conventional electronic components, such as front-end-of-line (FEOL) logic circuitry, micro/nano LEDs, and photodetectors without thermal damage. Together with the back-end-of-line (BEOL) transistors, use of poly-TMD leads to high transistor density, low power consumption, and small RC delay due to the shortened interconnects (Supporting information Fig. S1). The transferred TMDs has a strength in forming internal vias with reduced interconnect resistance and circuit clock speed compared to conventional technology that requires the formation of inter-tier vias. Therefore, internal vias made of transferred TMDs can play a significant role in monolithic 3D integration. Additionally, poly-TMD films can also function as sensors, such as photodetectors, due to their large surface-to-volume ratio and high photoresponsivity in the case of a monolayer.¹⁵ They are also an excellent memory cell transistor due to their high on-off switching with extremely low leakage characteristics.¹⁶ Furthermore, they are ideal for transparent electronics due to their atomic thickness.¹⁷ In summary, poly-TMD films are crucial materials for a wide range of industrial applications.

Despite their high potential, implement of 2D semiconductors in industry has been hindered by two major bottlenecks: 1) high contact resistance of TMD devices and 2) industrial scale processing, such as growth and transfer of CVD-grown TMDs. The junctions between 2D semiconductors and deposited metals have substantially high contact resistances owing to Fermi level pinning, resulting in discounting the on-current density.¹⁸ Furthermore, industrial scale processing of CVD-grown TMDs is still challenging owing to their ultra-thinness and low strength at grain boundaries.¹⁹ Although a number of strategies have been proposed to reduce the contact resistance for single-crystalline and pristine TMDs, there is a lack of studies on the junction between poly-TMDs and metals. It should be considered that both metal- and defect-induced gap states (MIGS and DIGS) are induced at the junction of metals and poly-TMDs, which have various defects, such as grain boundaries and bilayer patches. While low contact barrier by suppression of Fermi level pinning has been reported using semi-metals with limited density of states (DOS) and minimizing defect formation during metal deposition,^20–25 the poly-TMDs shows strong pinning effect of the Fermi level, leading to high contact resistance.^26,27 Therefore, novel approach is required to suppress both MIGS and DIGS for large-scale poly-TMDs for TFT applications.

In this study, we present an industrial solution to fabricate large-scale array of 2D MoS₂ FETs, wherein the polycrystalline MoS₂ is grown by metal-organic chemical vapor deposition (MOCVD). First, we successfully developed bottom-contact strategies to eliminate Schottky barrier completely at the poly-2D/metal interfaces in arrays of 2D FETs. As a result, the field-effect mobility and on-current of FETs resulted from vanishing Schottky barrier are excellent compared with other types of TFT channels and even compatible to those of their 2D single-crystalline counterparts. Second, we designed the fabrication processes to be suitable for uniform polycrystalline 2D monolayer MoS₂ grown by MOCVD on a 200 mm wafer scale, because the fully automated wet, photolithography and etching processes in our 200 mm fab facilities are too harsh for 2D materials to endure. Third, we utilized an automated transfer system to manipulate a 200-mm MoS₂ monolayer. We discovered that transferring poly-MoS₂ onto pre-patterned Au electrodes effectively suppresses deep-level pinning originating from the MIGS and induced shallow-level pinning originating from the DIGS, which reduces the barrier height to nearly zero. The best bottom-contact FET with a channel length of 500 nm exhibits a field-effect mobility (µ_FE) of 21 cm²/V·s, contact resistance (R_C) of 3.8 kΩ·µm, and I_on of 120 µA/µm at a bias of 1 V, comparable to conventional top-contacted MoS₂ flake-based FETs fabricated in the same fab facilities. In addition, minimizing the exposure of the contact interface of MoS₂ to fabrication processes by transferring it onto pre-patterned Au electrodes substantially reduces the variation in device performance. While the automated lift-off process utilizing NMP-based solvent with sonication can potentially induce peel-off of MoS₂, which may be detrimental to yield, employing the bottom contact strategy avoids the need for the lift-off process altogether, ensuring that MoS₂ remains intact and thereby providing an advantage as well. The high adhesion between Au and MoS₂ also safeguards that MoS₂ does not peel off during harsh wet processes, enhancing the device yield. In particular, the bottom-contact geometry is especially effective for M3D integration as it significantly reduces the lengths and spaces of the inter-tier vias, as illustrated in Fig. S1. With our 200-mm fab process, we have achieved a total yield of FET devices of 99.97% out of the devices measured from thousands of devices across the 200-mm Si wafer, together with high uniformity, despite of the small channel dimensions of the FETs.

To find out optimized device geometry for low R_C, we employed the density functional theory (DFT) calculations to predict the contact barrier heights at the junction between Au and MoS₂ in two cases: deposition of Au on top of MoS₂ and transfer of MoS₂ on top of Au. The Au is selected as a contact metal for several reasons: Firstly, the oxidation resistance of Au prevents formation of additional energy states at the junction. Secondly, the Au-MoS₂ interface has high adhesion energy (1.2 J/m²) compared to other metals,^28–31 leading to high device fabrication yield owing to conformal contact of the Au. Thirdly, small work function and high chemical stability of Au enables to fabricate n-type MoS₂ devices and stabilize the Au contacts in harsh processing conditions.³² To emulate the band structure at top contact (deposited Au contact) Au-MoS₂ interface, we relaxed the system to find a more stable state with energetic atoms, resulting in the Au-MoS₂ distance of 2.9 Å (Fig. 2a). Meanwhile, the bottom-contact is considered as a van der Waals (vdW) contact, where Au-MoS₂ distance is 3.5 Å owing to a vdW gap of 0.6 Å (Fig. 2b), as confirmed by high-angle annular dark-field scanning tunneling electron microscopy (HAADF-STEM) in Fig. S3. To emulate the polycrystallinity of MoS₂, we inserted sulfur vacancies. This is because the cell size is limited for emulating the grain boundaries, and it is thermodynamically stable that point defects, such as S-vacancies, are concentrated during the growth process near the strained grain boundaries or edges.^33,34 From the DFT simulations, the projected density of states (PDOS) were calculated near the Fermi level as shown in Fig. 2d and e for the top and bottom contact geometries, respectively. The vacancies in poly-MoS₂ significantly caused the gap states, i.e. DIGS, in both cases. Meanwhile, deep-level MIGS is induced only in the top contact geometry. In the bottom contact geometry, the larger interlayer distance at the vdW gap strongly suppresses the formation of MIGS. Thus, as depicted in Fig. 2g and h, the Fermi level (E_F) of metal is pinned around shallow and deeper levels at the top and bottom contact geometries, respectively, indicating that the Schottky barrier height (Φ_SB) for the bottom contact can be reduced. As we predicted from the DFT calculations, output curves (I_ds-V_ds) of two devices measured at 77 K in Fig. 2j and k showed that the bottom-contact device has an improved linearity and higher currents compared to the top-contact device. Since the dimensions of each device vary, the current has been normalized with respect to the channel length and width of each device. From temperature-dependent electrical measurements, we quantitatively extracted the Φ_SB using the Arrhenius equation for both cases. The Φ_SB of the top contact is 150 meV, while that of the bottom contact is nearly zero, as shown in Fig. 2m and n. For comparison, we used single crystal MoS₂ flake in the bottom contact geometry by transferring the exfoliated MoS₂ on the Au contacts (Fig. 2c). The DFT calculation of Fig. 2f shows that there is no gap state, consistent with formation of the vdW contacts with no Fermi level pinning effect.³⁵ However, the large Φ_SB of ~ 500 meV can be preserved, which corresponds to difference between work function of Au and electron affinity of single crystal MoS₂. The low-temperature measurement of the same device in Fig. 2l and o shows the non-linear output curves at 77 K and the Φ_SB of ~ 380 meV, which is similar to our DFT calculation and the previous report³⁵. Indeed, by combining the scalable synthesis method of poly-MoS₂ with the bottom contact strategy, it becomes feasible to achieve both high performance and large-scale production of 2D device arrays simultaneously. This integration allows for the practical fabrication of 2D device arrays that offer both excellent performance and a significant active area.

To fabricate device array with bottom-contact geometry in large scale, we developed the device fabrication process as shown in Fig. 3a. First, we successfully scaled up the growth of MoS₂ up to 200 mm in lateral size using a high-throughput MOCVD consisting of cold wall and showerhead.⁸ (See method for details) We then peeled off the entire MoS₂ layer grown on a 200-mm SiO₂/Si wafer using PMMA and thermal release tape (TRT) as an adhesive and a thermal releasing layer, respectively.⁶ The low adhesion energy between the as-grown MoS₂ and the SiO₂ originates from residual strain and use of automatic transfer machine substrate, as well as additional strain that arises from PMMA curing, enabling a 100% exfoliation yield. The host wafer is prepared by pre-patterning Ti/Au electrodes, followed by transferring MoS₂ onto it. The contact interface kept clean as the bottom side of the MoS₂ remains pristine after peeling-off and the top side of Au is cleaned by harsh wet and dry cleaning processes, as any impurity at the interface between MoS₂ and Au can degrade performance, increase variation, and lower the yield of the resulting TFT arrays. The height and the shape of the Au layer are engineered to achieve a high device yield. As shown in Fig. S9, both the mobility and yield decrease as the metal height increases. Therefore, the total thickness of the bottom-contact metal is maintained below 30 nm. Also, image-reversal resist photolithography was carried out to obtain an undercut profile, which helps create a smooth Au shape during the evaporation and prevents the tearing of MoS₂ during the transfer process. The final device structure is described in Fig. 3b-d. The top gate stack consists of 20 nm of Al₂O₃ or 10 nm of HfO₂ and 30 nm of Au for the top dielectrics and top gate metal, respectively. To verify whether the Φ_SB difference in Fig. 2 reflects the actual FET performance, a top-contact device with the same channel length and width as the bottom-contact FET was manufactured as a reference. For a fair comparison, the top-contact device was made with a back-gate structure, as described in the inset of Fig. 3e, where the gate and contact overlap in both devices. Consequently, the transfer curves of the two devices in Fig. 3e show that the bottom-contact FET has an order of magnitude higher on-current (I_on), as high as 84 µA/µm, compared to that of the top-contact FET. Field-effect mobility (µ_FE) of a bottom-contact FET was extracted as 18 cm²/V∙s, which is also an order of magnitude higher than that of the top-contact FET. If 10 nm HfO₂ is used as the top-gate dielectric, I_on and µ_FE are further enhanced to 120 µA/µm and 21 cm²/V∙s, respectively (Fig. S10). Based on the previous results, we can expect that the difference in Φ_SB between the two devices creates a difference in R_C that strongly affects device performance. The R_C extracted by the transmission line method (TLM) support the previous results, as shown in Fig. 3f. R_C of the bottom-contact device is extracted as 3.8 kΩ∙µm, while that of the top-contact FET is 42.6 kΩ∙µm. Moreover, the device performance in terms of field-effect mobility and on-current of the bottom-contact FET based on poly-MoS₂ is on par with that of a conventional top-contact device with single-crystal MoS₂ (Fig. S11). Therefore, good contact engineering helps overcome differences in the qualities of channel materials.

With the mass production of MoS₂ films becoming possible, arrays of bottom-contact and top-contact FETs were fabricated. Figure 4a depicts the difference in the transfer curves between the bottom-contact FETs and top-contact FETs. By normalizing the transfer curves with their respective channel lengths and widths, it is possible to eliminate the effects of variances in channel geometries, allowing for the focus to be solely on the inherent characteristics. The normalized I_on of both FETs, as calculated from the transfer curves of the two FETs plotted in Fig. 4b, provides a clearer representation of the differences between them. It was shown that the average I_on of the bottom-contact FETs was an order of magnitude higher than that of the top-contact FETs, corresponding to the previous FET performance comparison, due to the superior R_C of the bottom-contact FETs. Moreover, it is apparent that the variation in the bottom-contact FETs is much greater than that in the top-contact FETs. Differences were also observed in the field-effect mobility and threshold voltage, as shown in Fig. S12. A spatial analysis of bottom-contact FETs fabricated over a 200-mm wafer was carried out. Surprisingly, the device yield of the bottom contact was 99.97%, as shown in the wafer map in Fig. 4c, where only one device did not work. In addition, histograms are plotted in Fig. 4d, e, and f to show the device-to-device variances of V_th, normalized I_on, and SS, respectively. The die-to-die variances of the same parameters are also represented by the wafer maps in Fig. 4g, h, and i, indicating that the device performances are also uniform over 200 mm. This uniform MoS₂ FET fabrication can be attributed to the careful design of the process flow. First, automated transfer tools were adapted for a 200-mm MoS₂ monolayer, enabling the attachment and detachment of the MoS₂ film at a constant velocity to reduce the local strain. The strain affects the device performance and can also tear the film, particularly during transfer onto uneven substrates. To demonstrate this, we compared the MoS₂ transferred manually with MoS₂ transferred using an automatic tool (Fig. S13 and 14 for optical images and Raman analysis). Second, transferring MoS₂ on pre-patterned metal contact arrays minimizes exposure of MoS₂ to photolithographic contamination. Contamination at the contact site is crucial for device performance. Unlike conventional top-contact FETs, where contamination is inevitable, bottom-contact FETs do not have any impurities in their contacts. Finally, the strong adhesion between Au and S prevented MoS₂ from peeling off during the following processes, contributing to a yield close to 100%. Taken together, this study verifies that it contributes one step towards the practical TFT application of 2D material-based devices with a 100% device yield and excellent uniformity of MoS₂ FETs due to a simple bottom-contact configuration.

To summarize, our research has shown that 2D poly-MoS₂ FETs with an Au bottom-contact configuration demonstrate superior performance compared to conventional top-contact FETs. This performance improvement can be attributed to reduced contact resistance by suppressing the MIGS and pinning the Fermi level near the conduction band, thereby reducing the Schottky barrier to zero. Our study also revealed that key factors contributing to improved device variation, yield, and performance include the absence of impurities on the contact and the prevention of MoS₂ from peeling off due to the strong adhesion between Au and S. The bottom-contact FETs were shown to be uniform over the 200-mm wafer, with only a small die-to-die variation, indicating that the technique is ready for use in the current state. The potential impact of this development is significant, as it enables the creation of even more advanced and sophisticated electronic devices that were previously unattainable, offering superior performance compared to traditional TFTs.

MOCVD growth of 200-mm MoS₂

MoS₂ was grown in a shower-head-type cold-wall MOCVD reactor. Mo(CO)₆ (98%, Sigma Aldrich) and (C₂H₅)₂S₂ (99%, Sigma Aldrich) were used as the precursors of Mo and S, respectively. The flow rates of the precursors were 0.024 sccm for Mo(CO)₆, 0.99 sccm for (C₂H₅)₂S₂, and 100 sccm for H₂. The flow rates of precursors were regulated by individual mass flow controllers and electronic pressure controllers. The chamber pressure and wafer temperature were kept at 5.0 torr and 800^oC, respectively, during the growth process. We used pulsed injection strategy to regulate secondary nucleation and attain layer-by-layer growth mode. Each reaction cycle consisted of 2 min of co-injection of all the precursors, followed by interrupting the precursors and purging them for 1 min, resulting in a cycle time of 3 min. Wafer-scale poly-MoS₂ film was obtained with five growth cycles; thus, a total growth time of 15 min was required. A 200-mm Si wafer with 100-nm-thick thermal SiO₂ was used as the growth substrate.

Fabrication process of bottom-contact FETs

We began with a bare 200 mm Si wafer and created alignment marks by etching Si. After PR ashing, a 100 nm SiO₂ layer was formed by thermally oxidizing Si. Next, we deposited 10 nm of HfO₂ using a thermal ALD system at 150 ^oC to act as an etch stop when the top gate via was opened by wet etching. HfO₂ was chosen because it provides stronger adhesion to MoS₂ than other oxides.³¹ Following this, we patterned the bottom-contact source and drain electrodes using image-reversal PR processing to achieve smooth edges. For this process, we used AZ5214 for image-reversal PR, and the samples were baked at 95 ^oC for 5 min after exposure. Flood exposure was then performed for image reversal. Next, we deposited a 5/20 nm layer and finished by lift-off. To transfer the as-grown MoS₂ film, we coated it with PMMA and attached a TRT film. Using a semi-automatic transfer machine, we peeled the entire film stack of TRT / PMMA / MoS₂ from the substrate and attached it to the pre-patterned wafer. Our semi-auto-transfer machine was critical in achieving a high yield and uniformity of the MoS₂ film after transfer. After releasing TRT at 150 ^oC, we removed the PMMA film with acetone/isopropyl alcohol (IPA) in a single spin type wet station. It is important to note that O₂ plasma ashing at 180 ^oC for 90 s should be performed before transfer to completely remove contaminants on the Au surface and enhance adhesion. Finally, we deposited a top gate stack consisting of 20 nm of ALD Al₂O₃ or HfO₂ at 150 ^oC and 30 nm of Au top gate following the same patterning and deposition process as the source and drain electrodes. All fabrication processes, except for the semi-automatic transfer process, were performed in the 200-mm fab facilities at the Samsung Advanced Institute of Technology. Additional details are provided in the Supplementary Information (Fig. S8).

Electrical measurement of bottom-contact FETs

The room temperature single-device and wafer-scale device measurements presented in Figs. 3 and 4 were conducted with the assistance of a semi-automated probe station (SUMMIT 200, FormFactor) and a semiconductor parameter analyzer (Keithley 4200A, Tektronics). Additionally, the low-temperature device measurements depicted in Fig. 2 were carried out using a cryogenic probe station (CPX-VF, Lakeshore) and a semiconductor parameter analyzer (Keithley 4200, Tektronics).

DFT simulation

The electronic structures of the Au-MoS₂ contacts in the three types of FETs were determined using the Vienna Ab initio Simulation Package (VASP) and the density functional theory (DFT). A six-layer Au system (111) in contact with a monolayer of MoS₂ was constructed to form the Au-MoS₂ contact system. The dimension of the hetero-structure systems was maintained at 17.5 x 13.8 Å² with 216 Au atoms and 31 Mo/62 S atoms for a single crystal MoS₂. To obtain p-MoS₂, two S atoms were removed from the total sulfurs, resulting in a defect concentration of approximately 3%. To prevent interaction between neighboring cells, a 20 Å vacuum slab was employed. For the DFT calculations, we utilized the projector augmented wave method of the Perdew-Burke-Ernzerhof functional (PAW-PBE). The plane-wave basis set cutoff energy was set to 520 eV and the convergence threshold of 1 × 10^− 5 eV atom^− 1 was employed for total energy. Gamma k-space sampling of 30 × 30 × 1 was used for structural relaxation and 50 × 50 × 1 for DOS calculations.

Acknowledgements

This work was supported by Samsung Advanced Institute of Technology, Samsung Electronics Co., Ltd.

Author Contributions

J. Kwon, M. S., K. E. B., and J. Kim conceived the study. Kwon fabricated all the wafer-scale devices in this research and measured their electrical characteristics. M.S. produced wafer-scale MoS₂ films via MOCVD. J.Y. calculated the PDOS of various types of MoS₂-Au junctions using DFT calculations. H.R. helped fabricate a single-crystal MoS₂ FET by transferring a MoS₂/hBN stack onto the bottom electrodes under the guidance of G.-H.L. D.-S.K. analyzed the interfacial distances at different MoS₂-Au junctions using STEM. M.-H.L. provided a platform for the wafer-scale fabrication and electrical measurements of the MoS₂ bottom-contact FETs. E.K.L. assisted with the low-temperature electrical measurements and analysis. M.S.Y. provided guidance for the experimental demonstrations of the bottom-contact FETs. H. J. S. provided technical guidance and advice for proving this mechanism. J. Kwon, M. S. J. Kim, and K.-E.B. wrote the manuscript. All the authors contributed to the discussion.

Competing interests

All authors except for G.-H.L. are employed at Samsung Electronics Co. Ltd.

G.-H.L. declares no competing interests.

Data availability

All data generated or analyzed during this study are included in this published article and its Supplementary Information files. Data supporting the plots in this study are available from the corresponding authors upon reasonable request.

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Yes there is potential Competing Interest. All authors except for G.-H.L. are employed at Samsung Electronics Co. Ltd. G.-H.L. declares no competing interests.

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200-mm wafer scale integration of high performance polycrystalline MoS₂ thin film transistors

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Abstract

Figures

Main text

Methods

MOCVD growth of 200-mm MoS₂

Fabrication process of bottom-contact FETs

Electrical measurement of bottom-contact FETs

DFT simulation

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References

Additional Declarations

Supplementary Files

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Journal Publication

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200-mm wafer scale integration of high performance polycrystalline MoS2 thin film transistors

Status:

Journal Publication

Version 1

Abstract

Figures

Main text

Methods

MOCVD growth of 200-mm MoS2

Fabrication process of bottom-contact FETs

Electrical measurement of bottom-contact FETs

DFT simulation

Declarations

References

Additional Declarations

Supplementary Files

Status:

Journal Publication

Version 1

200-mm wafer scale integration of high performance polycrystalline MoS₂ thin film transistors

MOCVD growth of 200-mm MoS₂